H10W 20/037
The barrier, adhesion or liner layers being on top of a main
Official title: {the barrier, adhesion or liner layers being on top of a main fill metal}
H10W20/037 (The barrier, adhesion or liner layers being on top of a main) appears on 2,316 US grants and 2,634 published applications in this corpus.
Search patents in H10W- Granted patents
- 2,316
- Published applications
- 2,634
- Assignees
- 279
- Inventors
- 3,282
- Latest grant
- 8 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 2 | 0 |
| 1993 | 1 | 0 |
| 1994 | 3 | 0 |
| 1995 | 14 | 0 |
| 1996 | 5 | 0 |
| 1997 | 5 | 0 |
| 1998 | 9 | 0 |
| 1999 | 18 | 0 |
| 2000 | 39 | 0 |
| 2001 | 48 | 25 |
| 2002 | 54 | 50 |
| 2003 | 57 | 66 |
| 2004 | 74 | 105 |
| 2005 | 51 | 99 |
| 2006 | 46 | 118 |
| 2007 | 78 | 107 |
| 2008 | 69 | 125 |
| 2009 | 64 | 104 |
| 2010 | 105 | 93 |
| 2011 | 110 | 71 |
| 2012 | 80 | 75 |
| 2013 | 80 | 77 |
| 2014 | 80 | 75 |
| 2015 | 83 | 121 |
| 2016 | 102 | 95 |
| 2017 | 112 | 95 |
| 2018 | 105 | 106 |
| 2019 | 108 | 130 |
| 2020 | 112 | 142 |
| 2021 | 114 | 139 |
| 2022 | 106 | 154 |
| 2023 | 103 | 167 |
| 2024 | 105 | 132 |
| 2025 | 114 | 110 |
| 2026 | 59 | 53 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Dual damascene fully-aligned via interconnects with dual etch layers8 Sep 2026US 12,733,472 B2International Business Machines Corporation
- Carbon-based liner to reduce contact resistance25 Aug 2026US 12,721,119 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor structures with improved metal capping layers25 Aug 2026US 12,721,120 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Interconnect structure with dielectric cap layer and etch stop layer stack25 Aug 2026US 12,721,125 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Interconnect structure and methods of forming the same18 Aug 2026US 12,713,896 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Low resistance interconnect features and method for manufacturing the same8 Oct 2026US 2026/0314352 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Tunable w-shaped profile for structures8 Oct 2026US 2026/0314385 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Interconnection structure and method for fabricating the same8 Oct 2026US 2026/0314386 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Self-forming barrier for use in air gap formation1 Oct 2026US 2026/0305282 A1Adeia Semiconductor Solutions LLC
- Metal interconnects structures having modified interconnect interfaces1 Oct 2026US 2026/0305294 A1Intel Corporation
Most cited
By later US patents
- Method of forming metal layer using atomic layer deposition and semiconductor device having the metal layer as barrier metal layer or upper or lower electrode of capacitor1,063US 6,287,965 B1Samsung Electronics Co., Ltd. · 2001
- Selective electroless copper deposited interconnect plugs for ULSI applications638US 5,674,787 ASematech, Inc. · 1997
- Use of cobalt tungsten phosphide as a barrier material for copper metallization608US 5,695,810 ACornell Research Foundation, Inc. · 1997
- Forming capping layer over metal wire structure using selective atomic layer deposition590US 7,084,060 B1International Business Machines Corporation · 2006
- Selective formation of metallic films on metallic surfaces573US 8,956,971 B2ASM International N.V. · 2015