H10D 84/953
Sub-micron technology
Official title: {Sub-micron technology}
H10D84/953 (Sub-micron technology) appears on 68 US grants and 132 published applications in this corpus.
Search patents in H10D- Granted patents
- 68
- Published applications
- 132
- Assignees
- 19
- Inventors
- 239
- Latest grant
- 25 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2009 | 0 | 1 |
| 2010 | 0 | 30 |
| 2011 | 2 | 0 |
| 2012 | 4 | 1 |
| 2013 | 13 | 11 |
| 2014 | 21 | 4 |
| 2015 | 5 | 2 |
| 2016 | 2 | 1 |
| 2017 | 3 | 4 |
| 2018 | 3 | 3 |
| 2019 | 2 | 1 |
| 2020 | 4 | 2 |
| 2021 | 2 | 0 |
| 2022 | 0 | 2 |
| 2023 | 0 | 3 |
| 2024 | 0 | 7 |
| 2025 | 3 | 21 |
| 2026 | 4 | 39 |
By publication year. 2026 runs to 8 Oct.
Recent patents
- VTFET circuit with optimized MOL25 Aug 2026US 12,720,860 B2International Business Machines Corporation
- Semiconductor structure and method for manufacturing the same11 Aug 2026US 12,707,715 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device and method of fabricating the same4 Aug 2026US 12,701,787 B2Samsung Electronics Co., Ltd.
- Layout method and semiconductor structure for IC28 Jul 2026US 12,694,190 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device23 Sep 2025US 12,426,308 B2Samsung Electronics Co., Ltd.
- Semiconductor structure and method for manufacturing the same8 Oct 2026US 2026/0314066 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Integrated circuit device1 Oct 2026US 2026/0304952 A1Samsung Electronics Co., Ltd.
- Device leakage and yield for cells1 Oct 2026US 2026/0304953 A1QUALCOMM Incorporated
- Semiconductor structure1 Oct 2026US 2026/0304954 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device and method of fabricating the same13 Aug 2026US 2026/0239735 A1Samsung Electronics Co., Ltd.
Most cited
By later US patents
- Cross-coupled transistor layouts in restricted gate level layout architecture127US 7,956,421 B2Tela Innovations, Inc. · 2011
- Linear gate level cross-coupled transistor device with non-overlapping PMOS transistors and non-overlapping NMOS transistors relative to directions of gate electrodes87US 8,395,224 B2Tela Innovations, Inc. · 2013
- Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature82US 8,405,163 B2Tela Innovations, Inc. · 2013
- Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features inner extensions beyond gate electrode75US 8,575,706 B2Tela Innovations, Inc. · 2013
- Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts61US 8,847,329 B2Tela Innovations, Inc. · 2014