Cross-coupled transistor layouts in restricted gate level layout architecture

A cross-coupled transistor configuration within a semiconductor chip, comprising:

• a first P channel transistor including a first gate electrode defined in a gate level of a chip;
• a first N channel transistor including a second gate electrode defined in the gate level of the chip, wherein the second gate electrode of the first N channel transistor is electrically connected to the first gate electrode of the first P channel transistor;
• a second P channel transistor including a third gate electrode defined in the gate level of a chip;
• a second N channel transistor including a fourth gate electrode defined in the gate level of the chip, wherein the fourth gate electrode of the second N channel transistor is electrically connected to the third gate electrode of the second P channel transistor;
• and
• wherein each of the first P channel transistor, first N channel transistor, second P channel transistor, and second N channel transistor has a respective diffusion terminal electrically connected to a common node, and
• wherein each of the first, second, third, and fourth gate electrodes corresponds to a portion of an associated gate level feature defined within a corresponding gate level feature layout channel, and
• wherein each gate level feature is defined within its gate level feature layout channel without physically contacting another gate level feature defined within an adjoining gate level feature layout channel, and
• wherein the first gate electrode is electrically connected to the second gate electrode through at least one electrical conductor defined within a chip level other than the gate level, and
• wherein both the first and second P channel transistors are physically separated from each of the first and second N channel transistors.

A semiconductor chip, comprising:

• a first P channel transistor defined by a first gate electrode;
• a first N channel transistor defined by a second gate electrode;
• a second P channel transistor defined by a third gate electrode;
• and
• a second N channel transistor defined by a fourth gate electrode,
• wherein each of the first, second, third, and fourth gate electrodes is defined within a gate level of the semiconductor chip and is electrically associated with a common diffusion node,
• wherein the first gate electrode of the first P channel transistor is electrically connected to the second gate electrode of the first N channel transistor,
• wherein the third gate electrode of the second P channel transistor is electrically connected to the fourth gate electrode of the second N channel transistor,
• wherein each of the first, second, third, and fourth gate electrodes corresponds to a portion of an associated gate level feature defined within a corresponding gate level feature layout channel,
• wherein each gate level feature is defined within its gate level feature layout channel without physically contacting another gate level feature defined within an adjoining gate level feature layout channel,
• wherein each of the first, second, third, and fourth gate electrodes is defined to extend lengthwise in a first direction, and
• wherein the first and fourth gate electrodes are substantially co-aligned in the first direction, and
• wherein both the first and second P channel transistors are physically separated from each of the first and second N channel transistors.

A semiconductor chip, comprising:

• a first transistor of a first transistor type defined by a first gate electrode and a first diffusion region of a first diffusion type electrically connected to a common diffusion node;
• a first transistor of a second transistor type defined by a second gate electrode and a first diffusion region of a second diffusion type electrically connected to the common diffusion node;
• a second transistor of the first transistor type defined by a third gate electrode and a second diffusion region of the first diffusion type electrically connected to the common diffusion node;
• a second transistor of the second transistor type defined by a fourth gate electrode and a second diffusion region of the second diffusion type electrically connected to the common diffusion node,
• wherein the first and fourth gate electrodes are electrically connected to each other,
• wherein the second and third gate electrodes are electrically connected to each other,
• wherein each of the first, second, third, and fourth gate electrodes corresponds to a portion of an associated gate level feature defined within a corresponding gate level feature layout channel,
• wherein each gate level feature is defined within its gate level feature layout channel without physically contacting another gate level feature defined within an adjoining gate level feature layout channel,
• wherein the first, second, third, and fourth gate electrodes are respectively formed from physically separate gate level features, and
• wherein the first and second diffusion regions of the first diffusion type are physically separated from each of the first and second diffusion regions of the second diffusion type.