Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts

A method for creating a layout of an integrated circuit, comprising:

• operating a computer to define a layout of a first conductive gate level feature defined to form a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, the first conductive gate level feature defined to provide an electrical connection between the gate electrodes of the first transistor of the first transistor type and the first transistor of the second transistor type;
• operating the computer to define a layout of a second conductive gate level feature defined to form a gate electrode of a second transistor of the first transistor type;
• operating the computer to define a layout of a third conductive gate level feature defined to form a gate electrode of a second transistor of the second transistor type,
• wherein the gate electrodes of the first and second transistors of the first transistor type and of the first and second transistors of the second transistor type extend lengthwise in a parallel direction,
• wherein lengthwise centerlines of the gate electrodes of the first transistor of the first transistor type and the first transistor of the second transistor type are substantially aligned in the parallel direction,
• wherein the second and third gate level features are positioned on opposite sides of the first gate level feature;
• operating the computer to define a layout of diffusion regions of a first diffusion type defined to form the first and second transistors of the first transistor type;
• operating the computer to define a layout of diffusion regions of a second diffusion type defined to form the first and second transistors of the second transistor type, the diffusion regions of the first diffusion type collectively separated from the diffusion regions of the second diffusion type by a non-diffusion region, wherein each of the first and second transistors of the first transistor type and the first and second transistors of the second transistor type has a respective diffusion region to be electrically connected to a common node;
• operating the computer to define a layout of a first conductive contacting structure defined to connect to the second conductive gate level feature at a location not over the non-diffusion region;
• and
• operating the computer to define a layout of a second conductive contacting structure defined to connect to the third conductive gate level feature at a location not over the non-diffusion region, the third conductive gate level feature to be electrically connected to the second conductive gate level feature through the first and second conductive contacting structures, each of the first and second conductive contacting structures respectively defined as either a gate contact or a local interconnect structure.

A data storage device having program instructions stored thereon for generating a layout of an integrated circuit, comprising:

• program instructions for defining a layout of a first conductive gate level feature defined to form a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, the first conductive gate level feature defined to provide an electrical connection between the gate electrodes of the first transistor of the first transistor type and the first transistor of the second transistor type;
• program instructions for defining a layout of a second conductive gate level feature defined to form a gate electrode of a second transistor of the first transistor type;
• program instructions for defining a layout of a third conductive gate level feature defined to form a gate electrode of a second transistor of the second transistor type,
• wherein the gate electrodes of the first and second transistors of the first transistor type and of the first and second transistors of the second transistor type extend lengthwise in a parallel direction,
• wherein lengthwise centerlines of the gate electrodes of the first transistor of the first transistor type and the first transistor of the second transistor type are substantially aligned in the parallel direction,
• wherein the second and third gate level features are positioned on opposite sides of the first gate level feature;
• program instructions for defining a layout of diffusion regions of a first diffusion type defined to form portions of the first and second transistors of the first transistor type;
• program instructions for defining a layout of diffusion regions of a second diffusion type defined to form portions of the first and second transistors of the second transistor type, the diffusion regions of the first diffusion type collectively separated from the diffusion regions of the second diffusion type by a non-diffusion region, wherein each of the first and second transistors of the first transistor type and the first and second transistors of the second transistor type has a respective diffusion region to be electrically connected to a common node;
• program instructions for defining a layout of a first conductive contacting structure defined to connect to the second conductive gate level feature at a location not over the non-diffusion region;
• and
• program instructions for defining a layout of a second conductive contacting structure defined to connect to the third conductive gate level feature at a location not over the non-diffusion region, the third conductive gate level feature to be electrically connected to the second conductive gate level feature through the first and second conductive contacting structures, each of the first and second conductive contacting structures respectively defined as either a gate contact or a local interconnect structure.