US 2026/0304953 A1Published application

Device leakage and yield for cells

AssigneeQUALCOMM Incorporated

InventorsDeepika BALU, Jaseem AHAMMED, Hao WANG, Arun Kumar Kodigenahalli VENKATESWAR, Ashwin SETHURAM

Life of this patent

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Abstract

A chip includes gates extending in a first direction, wherein the gates are spaced apart in a second direction perpendicular to the first direction. The chip also includes a diffusion region extending in the second direction, wherein the gates extend across the diffusion region, the gates do not extend across another diffusion region, the diffusion region comprises bridge channels, and each of the bridge channels passes through a respective one of the gates. The chip also includes gate contacts, wherein each of the gate contacts is disposed on a respective one of the gates, and the gate contacts are located on one side of the diffusion region.

Claims30

Dependent claims

A chip, comprising:

first gates extending in a first direction, wherein the first gates are spaced apart in a second direction perpendicular to the first direction;
a first diffusion region extending in the second direction, wherein the first diffusion region comprises first bridge channels, and each of the first bridge channels passes through a respective one of the first gates;
first gate contacts, wherein each of the first gate contacts is disposed on a respective one of the first gates, and the first gate contacts are located on one side of the first diffusion region;
second gates extending in the first direction, wherein the second gates are spaced apart in the second direction, and the second gates are aligned with the first gates in the second direction;
a second diffusion region extending in the second direction, wherein the second diffusion region comprises second bridge channels, and each of the second bridge channels passes through a respective one of the second gates;
and
second gate contacts, wherein each of the second gate contacts is disposed on a respective one of the second gates, and the second gate contacts are located on one side of the second diffusion region.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/091,588Filed 26 Mar 2025
Published: 1 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 84/966
Connectability characteristics, i.e. diffusion and polysilicon geometries: gate electrode terminals or contacts
H03K 19/20
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits: characterised by logic function, e.g. AND, OR, NOR, NOT…
H10D 84/953
Technology used, i.e. design rules: sub-micron technology
H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts