US 12,694,190 B2Granted

Layout method and semiconductor structure for IC

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsChing-Yu Huang, Wei-Cheng Lin, Jiann-Tyng Tzeng

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Abstract

A layout method is provided. A timing analysis is performed based on design data of a standard cell to classify a plurality of device units of the standard cell into a timing-critical group and a non-timing-critical group. A plurality of first sources regions in the device units of the non-timing-critical group are aligned with a plurality of second sources regions in the device units of the timing-critical group in a first direction in floorplan of the standard cell in a layout. The device units of the timing-critical group are arranged in a first row of a cell array and the device units of the non-timing-critical group are arranged in a second row of the cell array. The first and second rows of the cell array share a common power line. First active regions of the first row are wider than second active regions of the second row.

Claims20

Dependent claims

A layout method for an integrated circuit, comprising:

receiving design data of a standard cell comprising a plurality of device units;
performing a timing analysis based on the design data to classify the device units into a timing-critical group and a non-timing-critical group, wherein the timing-critical group comprises the device units in a timing-critical path and the non-timing-critical group comprises the device units in a non-timing-critical path;
and
generating first floorplan of the standard cell in a layout, the generating comprising aligning a plurality of first sources regions of a plurality of first transistors in the device units of the non-timing-critical group with a plurality of second sources regions of a plurality of second transistors in the device units of the timing-critical group in a first direction in the layout in response to a number of the second transistors in the device units of the timing-critical group being determined as within a predetermined range,
wherein in the first floorplan, the device units of the timing-critical group are arranged in a first row of a cell array, and the device units of the non-timing-critical group are arranged in a second row of the cell array,
wherein the first and second rows of the cell array share a common power line extending in a second direction that is perpendicular to the first direction,
wherein a plurality of first active regions of the first row are wider than a plurality of second active regions of the second row, and one of the first active regions overlaps the common power line.

4 more elements

A layout method for an integrated circuit, comprising:

receiving a first design data of a first standard cell comprising a plurality of first device units;
receiving a second design data of a second standard cell comprising a plurality of second device units;
performing a timing analysis on the first design data to classify the first device units into a timing-critical group and a non-timing-critical group, wherein the timing-critical group comprises a first subset of the first device units in a timing-critical path and the non-timing-critical group comprises a second subset of the first device units in a non-timing-critical path;
aligning a plurality of first sources regions in the first device units of the non-timing-critical group with a plurality of second sources regions in the first device units of the timing-critical group in a first direction to thereby generate a first floorplan of the first standard cell in a layout, wherein in the first floorplan, the first subset of the first device units is arranged in a first row of a cell array, and the second subset of the first device units is arranged in a second row of the cell array;
and
arranging the second device units in the first and second rows of the cell array to generate a second floorplan of the second standard cell,
wherein the first and second rows of the cell array share a common power line extending in a second direction that is perpendicular to the first direction,
wherein in the first row, a first active region of the first device units is wider than a second active region of the second device units, and
wherein the first active region overlapping the common power line and the second active region non-overlapping the common power line have the same conductivity.

6 more elements

A semiconductor structure, comprising:

a plurality of standard cells arranged in a plurality of rows of a cell array, wherein one of the standard cells comprises a plurality of device units, and the device units are divided into a timing-critical group and a non-timing-critical group, wherein the timing-critical group comprises the device units in a timing-critical path and the non-timing-critical group comprises the device units in a non-timing-critical path,
wherein the device units of the timing-critical group are arranged in a first row of the cell array and the device units of the non-timing-critical group are arranged in a second row of the cell array, and the first and second rows of the cell array share a common power line,
wherein a plurality of first active regions of the first row are wider than a plurality of second active regions of the second row, and one of the first active regions overlaps the common power line.

Dependencies are inferred from the claim text.

Facts

Application: 18/403,683Filed 3 Jan 2024 · us provisional application
Priority: 22 Dec 2023
Published: US 2025/0217568 A13 Jul 2025
Granted: 28 Jul 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
H10D 84/907
Comprising field effect technology: cMOS gate arrays
H10D 84/953
Technology used, i.e. design rules: sub-micron technology
H10D 84/981
Layout specifications, i.e. inner core regions: power supply lines