Linear gate level cross-coupled transistor device with non-overlapping PMOS transistors and non-overlapping NMOS transistors relative to directions of gate electrodes

A method for creating a layout of an integrated circuit, comprising:

• operating a computer to define a gate electrode level region having a number of adjacently positioned gate electrode feature channels, each gate electrode feature channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate electrode feature channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends,
• wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,
• wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of only one transistor that is a second transistor of the first transistor type,
• wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of only one transistor that is a second transistor of the second transistor type,
• wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of only one transistor that is a third transistor of the first transistor type,
• wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of only one transistor that is a third transistor of the second transistor type,
• wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type,
• wherein the second, third, fourth, and fifth gate level features are positioned between the first and sixth gate level features in the second direction,
• wherein the second gate level feature is electrically connected to the fifth gate level feature, and wherein the third gate level feature is electrically connected to the fourth gate level feature,
• wherein each of the second and third transistors of the first transistor type and each of the second and third transistors of the second transistor type has a respective diffusion region electrically connected to a common node,
• wherein the first, second, third, and fourth transistors of the first transistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region,
• wherein the gate electrode of the second transistor of the first transistor type is substantially co-aligned with the gate electrode of the second transistor of the second transistor type along a first common line of extent in the first direction, and wherein the second gate level feature includes an inner end located within the inner portion of the gate electrode level region, and wherein the third gate level feature includes an inner end located within the inner portion of the gate electrode level region, and wherein the inner end of the second gate level feature is separated from the inner end of the third gate level feature by a first line end spacing as measured in the first direction,
• wherein the gate electrode of the third transistor of the first transistor type is substantially co-aligned with the gate electrode of the third transistor of the second transistor type along a second common line of extent in the first direction, and wherein the fourth gate level feature includes an inner end located within the inner portion of the gate electrode level region, and wherein the fifth gate level feature includes an inner end located within the inner portion of the gate electrode level region, and wherein the inner end of the fourth gate level feature is separated from the inner end of the fifth gate level feature by a second line end spacing as measured in the first direction,
• wherein either the inner ends of the second and fourth gate level features are offset from each other in the first direction, or the inner ends of the third and fifth gate level features are offset from each other in the first direction, or the inner ends of the second and fourth gate level features are offset from each other in the first direction and inner ends of the third and fifth gate level features are offset from each other in the first direction.

A data storage device having program instructions stored thereon for generating a layout of an integrated circuit, comprising:

• program instructions for defining a gate electrode level region having a number of adjacently positioned gate electrode feature channels, each gate electrode feature channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate electrode feature channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends,
• wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,
• wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of only one transistor that is a second transistor of the first transistor type,
• wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of only one transistor that is a second transistor of the second transistor type,
• wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of only one transistor that is a third transistor of the first transistor type,
• wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of only one transistor that is a third transistor of the second transistor type,
• wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type,
• wherein the second, third, fourth, and fifth gate level features are positioned between the first and sixth gate level features in the second direction,
• wherein the second gate level feature is electrically connected to the fifth gate level feature and wherein the third gate level feature is electrically connected to the fourth gate level feature,
• wherein each of the second and third transistors of the first transistor type and each of the second and third transistors of the second transistor type has a respective diffusion region electrically connected to a common node,
• wherein the first, second, third, and fourth transistors of the first transistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region,
• wherein the gate electrode of the second transistor of the first transistor type is substantially co-aligned with the gate electrode of the second transistor of the second transistor type along a first common line of extent in the first direction, and wherein the second gate level feature includes an inner end located within the inner portion of the gate electrode level region, and wherein the third gate level feature includes an inner end located within the inner portion of the gate electrode level region, and wherein the inner end of the second gate level feature is separated from the inner end of the third gate level feature by a first line end spacing as measured in the first direction,
• wherein the gate electrode of the third transistor of the first transistor type is substantially co-aligned with the gate electrode of the third transistor of the second transistor type along a second common line of extent in the first direction, and wherein the fourth gate level feature includes an inner end located within the inner portion of the gate electrode level region, and wherein the fifth gate level feature includes an inner end located within the inner portion of the gate electrode level region, and wherein the inner end of the fourth gate level feature is separated from the inner end of the fifth gate level feature by a second line end spacing as measured in the first direction,
• wherein either the inner ends of the second and fourth gate level features are offset from each other in the first direction, or the inner ends of the third and fifth gate level features are offset from each other in the first direction, or the inner ends of the second and fourth gate level features are offset from each other in the first direction and inner ends of the third and fifth gate level features are offset from each other in the first direction.