Semiconductor device

A semiconductor device, comprising:

• a first active pattern and a second active pattern on a substrate;
• a pair of first source/drain patterns on the first active pattern and a first channel pattern between the first source/drain patterns;
• a pair of second source/drain patterns on the second active pattern and a second channel pattern between the second source/drain patterns, each of the first and second channel patterns comprising semiconductor patterns, which are spaced apart from each other in a stacked formation;
• a gate electrode on the first and second channel patterns;
• a first gate cutting pattern adjacent to the first channel pattern that penetrates the gate electrode;
• and
• a first spacer pattern between the first gate cutting pattern and the first channel pattern,
• wherein the first spacer pattern comprises:
• a first remaining pattern adjacent to an outermost side surface of at least one of the semiconductor patterns;
• and
• a second remaining pattern on the first remaining pattern,
• wherein the first and second remaining patterns comprise different materials from each other,
• wherein the gate electrode comprises a first extended portion, which is in an upper portion thereof and overlaps the first spacer pattern in a direction generally perpendicular to a plane defined by the substrate, and a protruding portion, which is on the first extended portion, and
• wherein a height of a top surface of the protruding portion increases with decreasing distance to the first gate cutting pattern.

A semiconductor device, comprising:

• a first active pattern and a second active pattern on a substrate;
• a pair of first source/drain patterns on the first active pattern and a first channel pattern between the first source/drain patterns;
• a pair of second source/drain patterns on the second active pattern and a second channel pattern between the second source/drain patterns, each of the first and second channel patterns comprising semiconductor patterns, which are spaced apart from each other in a stacked formation;
• a gate electrode on the first and second channel patterns;
• a gate insulating layer interposed between the first and second channel patterns and the gate electrode;
• a gate spacer on at least one side surface of the gate electrode;
• a first gate cutting pattern provided adjacent to the first channel pattern that penetrates the gate electrode;
• a second gate cutting pattern adjacent to the second channel pattern that penetrates the gate electrode;
• a first spacer pattern between the first gate cutting pattern and the first channel pattern;
• a gate capping pattern on the gate electrode and the first and second gate cutting patterns;
• an interlayer insulating layer on the gate capping pattern;
• an active contact that penetrates the interlayer insulating layer and is electrically connected to at least one of the first and second source/drain patterns;
• a gate contact that penetrates the interlayer insulating layer and the gate capping pattern and is electrically connected to the gate electrode;
• a first metal layer on the interlayer insulating layer, the first metal layer comprising first and second power lines, which are on the first and second gate cutting patterns, respectively, and first interconnection lines, which are between the first and second power lines, the first interconnection lines being electrically connected to the active contact and the gate contact;
• and
• a second metal layer on the first metal layer,
• wherein the second metal layer comprises second interconnection lines, which are electrically connected to the first metal layer,
• wherein the first spacer pattern comprises:
• a first remaining pattern adjacent to an outermost side surface of at least one of the semiconductor patterns of the first channel pattern;
• and
• a second remaining pattern on the first remaining pattern,
• wherein the first and second remaining patterns comprise different materials from each other, and
• wherein the second remaining pattern is spaced apart from the first gate cutting pattern.