H10D 84/951
Technology used, i.e. design rules
Official title: {Technology used, i.e. design rules}
H10D84/951 (Technology used, i.e. design rules) appears on 164 US grants and 244 published applications in this corpus.
Search patents in H10D- Granted patents
- 164
- Published applications
- 244
- Assignees
- 23
- Inventors
- 300
- Latest grant
- 25 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2007 | 0 | 1 |
| 2008 | 1 | 0 |
| 2009 | 0 | 2 |
| 2010 | 1 | 88 |
| 2011 | 18 | 0 |
| 2012 | 45 | 1 |
| 2013 | 15 | 19 |
| 2014 | 24 | 4 |
| 2015 | 7 | 4 |
| 2016 | 6 | 5 |
| 2017 | 4 | 9 |
| 2018 | 9 | 8 |
| 2019 | 4 | 6 |
| 2020 | 5 | 4 |
| 2021 | 5 | 4 |
| 2022 | 1 | 5 |
| 2023 | 2 | 4 |
| 2024 | 5 | 12 |
| 2025 | 6 | 26 |
| 2026 | 6 | 42 |
By publication year. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- VTFET circuit with optimized MOL25 Aug 2026US 12,720,860 B2International Business Machines Corporation
- Semiconductor structure and method for manufacturing the same11 Aug 2026US 12,707,715 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device and method of fabricating the same4 Aug 2026US 12,701,787 B2Samsung Electronics Co., Ltd.
- Layout method and semiconductor structure for IC28 Jul 2026US 12,694,190 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Area-efficient fully depleted semiconductor-on-insulator structure with mixed threshold voltage transistors7 Jul 2026US 12,677,477 B2GLOBALFOUNDRIES U. S. Inc.
- Semiconductor structure and method for manufacturing the same8 Oct 2026US 2026/0314066 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Integrated circuit device1 Oct 2026US 2026/0304952 A1Samsung Electronics Co., Ltd.
- Device leakage and yield for cells1 Oct 2026US 2026/0304953 A1QUALCOMM Incorporated
- Semiconductor structure1 Oct 2026US 2026/0304954 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Area-efficient fully depleted semiconductor-on-insulator structure with mixed threshold voltage transistors10 Sep 2026US 2026/0271398 A1GLOBALFOUNDRIES U. S. Inc.
Most cited
By later US patents
- Dynamic array architecture227US 7,446,352 B2Tela Innovations, Inc. · 2008
- Integrated circuit having gate electrode level region including at least four linear-shaped conductive structures with some outer-contacted linear-shaped conductive structures having larger outer extending portion than inner extending portion159US 8,134,184 B2Tela Innovations, Inc. · 2012
- Dynamic array architecture142US 7,842,975 B2Tela Innovations, Inc. · 2010
- Semiconductor device having at least three linear-shaped electrode level conductive features of equal length positioned side-by-side at equal pitch141US 8,058,671 B2Tela Innovations, Inc. · 2011
- Semiconductor device and associated layouts having transistors formed from linear conductive segment with non-active neighboring linear conductive segment140US 7,910,958 B2Tela Innovations, Inc. · 2011