Integrated circuit device

An integrated circuit device comprising:

• a first logic cell region and a second logic cell region adjacent to one another in a first horizontal direction;
• a plurality of first logic cells arranged in portions of the first logic cell region and the second logic cell region, each of the plurality of first logic cells having a first cell height;
• and
• at least one second logic cell arranged in another portion of the second logic cell region and having a second cell height greater than the first cell height,
• wherein the first logic cells arranged in the first logic cell region among the plurality of first logic cells are arranged in a second horizontal direction substantially orthogonal to the first horizontal direction,
• wherein the first logic cells arranged in the second logic cell region among the plurality of first logic cells are arranged on both sides of the at least one second logic cell in the second horizontal direction,
• wherein each of the plurality of first logic cells comprises a first n-channel field effect transistor (FET) (NFET) and a first p-channel FET (PFET),
• wherein the at least one second logic cell comprises a second NFET and a second PFET, and
• wherein a channel width of each of the second NFET and the second PFET is greater than a channel width of each of the first NFET and the first PFET, and
• wherein both ends of the at least one second logic cell in the second horizontal direction are aligned, in the first horizontal direction, with one end of both ends in the second horizontal direction of one first logic cell arranged in the first logic cell region among the plurality of first logic cells and another end of both ends in the second horizontal direction of another first logic cell arranged in the first logic cell region among the plurality of first logic cells.

An integrated circuit device comprising:

• a first logic cell region and a second logic cell region adjacent to one another in a first horizontal direction;
• a plurality of gate electrodes configured to extend in the first logic cell region and the second logic cell region in a second horizontal direction substantially orthogonal to the first horizontal direction;
• a plurality of first logic cells arranged in portions of the first logic cell region and the second logic cell region, each of the plurality of first logic cells having a first cell height in the second horizontal direction;
• and
• at least one second logic cell arranged in another portion of the second logic cell region and having a second cell height greater than the first cell height in the second horizontal direction,
• wherein the first logic cells arranged in the first logic cell region among the plurality of first logic cells are arranged in the second horizontal direction,
• wherein the first logic cells arranged in the second logic cell region among the plurality of first logic cells are arranged on both sides of the at least one second logic cell in the second horizontal direction,
• wherein each of the plurality of first logic cells comprises a first nanosheet stacked structure including nanosheets arranged in portions overlapping any one of the plurality of gate electrodes in a vertical direction, sequentially apart from one another in the vertical direction, and having a first channel width, and a first source/drain region connected to the nanosheets included in the first nanosheet stacked structure,
• wherein the at least one second logic cell comprises a second nanosheet stacked structure including nanosheets arranged in portions overlapping any one of the plurality of gate electrodes in the vertical direction, sequentially apart from one another in the vertical direction, and having a second channel width greater than the first channel width, and a second source/drain region connected to the nanosheets included in the second nanosheet stacked structure, and
• wherein one end of both ends in the second horizontal direction of the at least one second logic cell is aligned in the first horizontal direction with one end of both ends in the second horizontal direction of one first logic cell arranged in the first logic cell region among the plurality of first logic cells, and another end of the both ends in the second horizontal direction of the at least one second logic cell is aligned in the first horizontal direction with the other end of the both ends in the second horizontal direction of another first logic cell arranged in the first logic cell region among the plurality of first logic cells.