Area-efficient fully depleted semiconductor-on-insulator structure with mixed threshold voltage transistors

A structure comprising:

• an insulator layer on a semiconductor substrate;
• multiple well regions in the semiconductor substrate adjacent to the insulator layer and including:
• an Nwell;
• a Pwell laterally surrounded by the Nwell;
• an additional Nwell in the semiconductor substrate below the multiple well regions;
• and
• rows of field effect transistors on the insulator layer and including, above each well region, a row of P-channel field effect transistors and a row of N-channel field effect transistors,
• wherein the Nwell is electrically connected to receive a first bias voltage, and
• wherein the Pwell is electrically connected to receive a second bias voltage that is lower than the first bias voltage.

A structure comprising:

• an insulator layer on a semiconductor substrate;
• multiple well regions in the semiconductor substrate adjacent to the insulator layer, wherein the multiple well regions include alternating Nwells and Pwells, and wherein at least one well region of the multiple well regions includes an extension extending laterally into an adjacent well region;
• an additional Nwell in the semiconductor substrate below the multiple well regions;
• and
• rows of N-channel field effect transistors and P-channel field effect transistors on the insulator layer above the Nwells and the Pwells, respectively,
• wherein at least one of:
• a row of N-channel field effect transistors includes at least one N-channel field effect transistor on the insulator layer above a P-type extension of a Pwell;
• and
• a row of P-channel field effect transistors includes at least one P-channel field effect transistor on the insulator layer above an N-type extension of an Nwell,
• wherein the Nwells and any N-type extension thereof are electrically connected to receive a first bias voltage, and
• wherein the Pwells and any P-type extension thereof are electrically connected to receive a second bias voltage that is lower than the first bias voltage.