Integrated circuit having gate electrode level region including at least four linear-shaped conductive structures with some outer-contacted linear-shaped conductive structures having larger outer extending portion than inner extending portion

A method for creating a layout of an integrated circuit, comprising:

• operating a computer to define a layout of a gate electrode level region to include four linear conductive structure layout shapes each formed to extend lengthwise in a first direction, wherein each of the four linear conductive structure layout shapes is positioned within an area of the layout of the gate electrode level region having a radius up to about 965 nanometers, wherein the four linear conductive structure layout shapes include—
• a first linear conductive structure layout shape having one gate portion, a first extending portion, and a second extending portion, wherein the first and second extending portions of the first linear conductive structure layout shape extend in the first direction in opposite directions away from the gate portion of the first linear conductive structure layout shape, wherein the gate portion of the first linear conductive structure layout shape forms a gate electrode of a first transistor of a first transistor type,
• a second linear conductive structure layout shape having one gate portion, a first extending portion, and a second extending portion, wherein the first and second extending portions of the second linear conductive structure layout shape extend in the first direction in opposite directions away from the gate portion of the second linear conductive structure layout shape, wherein the gate portion of the second linear conductive structure layout shape forms a gate electrode of a first transistor of a second transistor type,
• a third linear conductive structure layout shape having one gate portion, a first extending portion, and a second extending portion, wherein the first and second extending portions of the third linear conductive structure layout shape extend in the first direction in opposite directions away from the gate portion of the third linear conductive structure layout shape, wherein the gate portion of the third linear conductive structure layout shape forms a gate electrode of a second transistor of the first transistor type,
• a fourth linear conductive structure layout shape having one gate portion, a first extending portion, and a second extending portion, wherein the first and second extending portions of the fourth linear conductive structure layout shape extend in the first direction in opposite directions away from the gate portion of the fourth linear conductive structure layout shape, wherein the gate portion of the fourth linear conductive structure layout shape forms a gate electrode of a second transistor of the second transistor type,
• wherein the first and second transistors of the first transistor type are separated from the first and second transistors of the second transistor type by a non-diffusion area of a substrate region located between transistors of the first transistor type and transistors of the second transistor type,
• wherein the first extending portions of the first, second, third, and fourth linear conductive structure layout shapes extend over the non-diffusion area of the substrate region, and wherein the second extending portions of the first, second, third, and fourth linear conductive structure layout shapes extend away from the non-diffusion area of the substrate region,
• wherein at least one of the first, second, third, and fourth linear conductive structure layout shapes is an inner-contacted conductive structure layout shape having its first extending portion at least partially overlapped by a contacting structure layout shape at a location over the non-diffusion area of the substrate region,
• wherein at least one of the first, second, third, and fourth linear conductive structure layout shapes is an outer-contacted conductive structure layout shape having its second extending portion at least partially overlapped by a contacting structure layout shape at a location away from the non-diffusion area of the substrate region, and
• wherein at least one of the first, second, third, and fourth linear conductive structure layout shapes that is one of the outer-contacted conductive structure layout shapes has a length of its second extending portion as measured in the first direction greater than a length of its first extending portion as measured in the first direction.

A computer readable medium having computer executable program instructions stored thereon for creating a layout of an integrated circuit, comprising:

• program instructions for defining a layout of a gate electrode level region to include four conductive structure layout shapes each formed to extend lengthwise in a first direction, wherein each of the four linear conductive structure layout shapes is positioned within an area of the layout of the gate electrode level region having a radius up to about 965 nanometers, wherein the four linear conductive structure layout shapes include—
• a first linear conductive structure layout shape having one gate portion, a first extending portion, and a second extending portion, wherein the first and second extending portions of the first linear conductive structure layout shape extend in the first direction in opposite directions away from the gate portion of the first linear conductive structure layout shape, wherein the gate portion of the first linear conductive structure layout shape forms a gate electrode of a first transistor of a first transistor type,
• a second linear conductive structure layout shape having one gate portion, a first extending portion, and a second extending portion, wherein the first and second extending portions of the second linear conductive structure layout shape extend in the first direction in opposite directions away from the gate portion of the second linear conductive structure layout shape, wherein the gate portion of the second linear conductive structure layout shape forms a gate electrode of a first transistor of a second transistor type,
• a third linear conductive structure layout shape having one gate portion, a first extending portion, and a second extending portion, wherein the first and second extending portions of the third linear conductive structure layout shape extend in the first direction in opposite directions away from the gate portion of the third linear conductive structure layout shape, wherein the gate portion of the third linear conductive structure layout shape forms a gate electrode of a second transistor of the first transistor type,
• a fourth linear conductive structure layout shape having one gate portion, a first extending portion, and a second extending portion, wherein the first and second extending portions of the fourth linear conductive structure layout shape extend in the first direction in opposite directions away from the gate portion of the fourth linear conductive structure layout shape, wherein the gate portion of the fourth linear conductive structure layout shape forms a gate electrode of a second transistor of the second transistor type,
• wherein the first and second transistors of the first transistor type are separated from the first and second transistors of the second transistor type by a non-diffusion area of a substrate region located between transistors of the first transistor type and transistors of the second transistor type,
• wherein the first extending portions of the first, second, third, and fourth linear conductive structure layout shapes extend over the non-diffusion area of the substrate region, and wherein the second extending portions of the first, second, third, and fourth linear conductive structure layout shapes extend away from the non-diffusion area of the substrate region,
• wherein at least one of the first, second, third, and fourth linear conductive structure layout shapes is an inner-contacted conductive structure layout shape having its first extending portion at least partially overlapped by a contacting structure layout shape at a location over the non-diffusion area of the substrate region,
• wherein at least one of the first, second, third, and fourth linear conductive structure layout shapes is an outer-contacted conductive structure layout shape having its second extending portion at least partially overlapped by a contacting structure layout shape at a location away from the non-diffusion area of the substrate region, and
• wherein at least one of the first, second, third, and fourth linear conductive structure layout shapes that is one of the outer-contacted conductive structure layout shapes has a length of its second extending portion as measured in the first direction greater than a length of its first extending portion as measured in the first direction.