VTFET circuit with optimized MOL

An integrated circuit (IC) device comprising:

• a logic circuit comprising at least two formed Vertical Transport Field Effect Transistor (VTFET) devices, each VTFET device having corresponding a source region, a drain region, and a gate region;
• an inter-level dielectric material stack formed above terminals corresponding to each region of the at least two VTFET devices;
• a first metallization level including a first level metal line above the at least two VTFET devices;
• a first level conductive contact structure formed at a first level within said inter-level dielectric material stack below the first level metal line and having a first end contacting one of:
• the source region, the drain region, or the gate region of a first VTFET device, the first level conductive contact structure having a second end connecting to one of:
• a source region, a drain region, or a gate region of a second of the VTFET device of the logic circuit;
• and
• a second level conductive contact structure formed at a second level within said inter-level dielectric material stack below the first level metal line, a top surface of the second level conductive contact structure being below a bottom surface of the first level metal line and not touching the bottom surface of the first level metal line, and the second level conductive contact structure having at least one end directly contacting the first level conductive contact structure, wherein the second level conductive contact structure is disposed above the first level conductive contact structure.