US 8,405,163 B2Granted

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature

AssigneeTela Innovations, Inc.

InventorsScott T. Becker, Jim Mali, Carole Lambert

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Abstract

A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.

Claims24

Dependent claims

An integrated circuit, comprising:

a gate electrode level region having a number of adjacently positioned gate level feature layout channels, each gate level feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate level feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a line end spacing and a second end located adjacent to another line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends,
wherein the gate electrode level region includes a first gate level feature that includes a first part that forms a gate electrode of a first transistor of a first transistor type and a second part that forms a gate electrode of a first transistor of a second transistor type, wherein the gate electrode of the first transistor of the first transistor type is substantially co-aligned with the gate electrode of the first transistor of the second transistor type along a first common line of extent in the first direction, and wherein the gate electrode of the first transistor of the first transistor type is electrically connected to the gate electrode of the first transistor of the second transistor type through the first gate level feature,
wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type,
wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type,
wherein the second and third gate level features are located in different gate level feature layout channels,
wherein gate electrode of the second transistor of the first transistor type is electrically connected to the gate electrode of the second transistor of the second transistor type,
wherein the first and second transistors of the first transistor type are collectively separated from the first and second transistors of the second transistor type by an inner portion of the gate electrode level region,
wherein each of the first and second transistors of the first transistor type is formed in part by a shared diffusion region of a first diffusion type located on a first side of the first gate level feature,
wherein each of the first and second transistors of the second transistor type is formed in part by a shared diffusion region of a second diffusion type located on a second side of the first gate level feature,
wherein each of the shared diffusion region of the first diffusion type and the shared diffusion region of the second diffusion type is electrically connected to a common node, and
wherein the first and second sides of the first gate level feature are opposite sides of the first gate level feature.

8 more elements

A method for creating a layout of an integrated circuit, comprising:

operating a computer to define a gate electrode level region having a number of adjacently positioned gate level feature layout channels, each gate level feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate level feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a line end spacing and a second end located adjacent to another line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends,
wherein the gate electrode level region includes a first gate level feature that includes a first part that forms a gate electrode of a first transistor of a first transistor type and a second part that forms a gate electrode of a first transistor of a second transistor type, wherein the gate electrode of the first transistor of the first transistor type is substantially co-aligned with the gate electrode of the first transistor of the second transistor type along a first common line of extent in the first direction, and wherein the gate electrode of the first transistor of the first transistor type is electrically connected to the gate electrode of the first transistor of the second transistor type through the first gate level feature,
wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type,
wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type,
wherein the second and third gate level features are located in different gate level feature layout channels,
wherein gate electrode of the second transistor of the first transistor type is electrically connected to the gate electrode of the second transistor of the second transistor type,
wherein the first and second transistors of the first transistor type are collectively separated from the first and second transistors of the second transistor type by an inner portion of the gate electrode level region,
wherein each of the first and second transistors of the first transistor type is formed in part by a shared diffusion region of a first diffusion type located on a first side of the first gate level feature,
wherein each of the first and second transistors of the second transistor type is formed in part by a shared diffusion region of a second diffusion type located on a second side of the first gate level feature,
wherein each of the shared diffusion region of the first diffusion type and the shared diffusion region of the second diffusion type is electrically connected to a common node, and
wherein the first and second sides of the first gate level feature are opposite sides of the first gate level feature.

8 more elements

A data storage device having program instructions stored thereon for generating a layout of an integrated circuit, comprising:

program instructions for defining a gate electrode level region having a number of adjacently positioned gate level feature layout channels, each gate level feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate level feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a line end spacing and a second end located adjacent to another line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends,
wherein the gate electrode level region includes a first gate level feature that includes a first part that forms a gate electrode of a first transistor of a first transistor type and a second part that forms a gate electrode of a first transistor of a second transistor type, wherein the gate electrode of the first transistor of the first transistor type is substantially co-aligned with the gate electrode of the first transistor of the second transistor type along a first common line of extent in the first direction, and wherein the gate electrode of the first transistor of the first transistor type is electrically connected to the gate electrode of the first transistor of the second transistor type through the first gate level feature,
wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type,
wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type,
wherein the second and third gate level features are located in different gate level feature layout channels,
wherein gate electrode of the second transistor of the first transistor type is electrically connected to the gate electrode of the second transistor of the second transistor type,
wherein the first and second transistors of the first transistor type are collectively separated from the first and second transistors of the second transistor type by an inner portion of the gate electrode level region,
wherein each of the first and second transistors of the first transistor type is formed in part by a shared diffusion region of a first diffusion type located on a first side of the first gate level feature,
wherein each of the first and second transistors of the second transistor type is formed in part by a shared diffusion region of a second diffusion type located on a second side of the first gate level feature,
wherein each of the shared diffusion region of the first diffusion type and the shared diffusion region of the second diffusion type is electrically connected to a common node, and
wherein the first and second sides of the first gate level feature are opposite sides of the first gate level feature.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/753,798Filed 2 Apr 2010 · continuation
Priority: 13 Mar 2008
Published: US 2010/0187623 A129 Jul 2010
Granted: 26 Mar 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification23 codes

H10D 84/907
Comprising field effect technology: cMOS gate arrays
G06F 30/39
Circuit design: circuit design at the physical level
G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…

Family

Application61/036,460Us provisional application · filed 13 Mar 2008
Application61/042,709Us provisional application · filed 4 Apr 2008
Application61/045,953Us provisional application · filed 17 Apr 2008
Application61/050,136Us provisional application · filed 2 May 2008
Application12/402,465Parent of this continuation · filed 11 Mar 2009
US 2010/0187623 A1Pre-grant publication · published 29 Jul 2010
US 7,956,421 B2Parent of this continuation
US 2009/0224317 A1Published application
US 8,405,163 B2This patent

From the US filing history. Foreign family members aren’t listed.