H10D 62/8163
Comprising long-range structurally-disordered materials
Official title: {comprising long-range structurally-disordered materials, e.g. one-dimensional vertical amorphous superlattices}
H10D62/8163 (Comprising long-range structurally-disordered materials) appears on 32 US grants and 27 published applications in this corpus.
Search patents in H10D- Granted patents
- 32
- Published applications
- 27
- Assignees
- 20
- Inventors
- 68
- Latest grant
- 1 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1987 | 3 | 0 |
| 1988 | 1 | 0 |
| 1989 | 2 | 0 |
| 1990 | 1 | 0 |
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 2 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 0 | 0 |
| 2000 | 1 | 0 |
| 2001 | 2 | 0 |
| 2002 | 0 | 1 |
| 2003 | 0 | 0 |
| 2004 | 0 | 0 |
| 2005 | 0 | 1 |
| 2006 | 1 | 0 |
| 2007 | 1 | 0 |
| 2008 | 0 | 1 |
| 2009 | 0 | 0 |
| 2010 | 0 | 0 |
| 2011 | 1 | 0 |
| 2012 | 0 | 1 |
| 2013 | 0 | 0 |
| 2014 | 0 | 2 |
| 2015 | 1 | 2 |
| 2016 | 4 | 3 |
| 2017 | 2 | 3 |
| 2018 | 3 | 3 |
| 2019 | 1 | 1 |
| 2020 | 2 | 2 |
| 2021 | 0 | 0 |
| 2022 | 1 | 0 |
| 2023 | 0 | 3 |
| 2024 | 1 | 2 |
| 2025 | 0 | 2 |
| 2026 | 1 | 0 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Source drain formation in gate all around transistor1 Sep 2026US 12,727,214 B2APPLIED Materials.Inc.
- Methods of forming bottom dielectric isolation layers17 Dec 2024US 12,170,230 B2APPLIED Materials.Inc.
- Method for making superlattice structures with reduced defect densities30 Aug 2022US 11,430,869 B2Atomera Incorporated
- Method for making superlattice structures with reduced defect densities20 Oct 2020US 10,811,498 B2Atomera Incorporated
- Cascade tunneling field effect transistors1 Sep 2020US 10,763,367 B2Purdue Research Foundation
- Method of fabricating semiconductor devices with isolated superlattice structures17 Apr 2025US 2025/0125149 A1Atomera Incorporated
- Methods of forming bottom dielectric isolation layers13 Feb 2025US 2025/0056871 A1APPLIED Materials.Inc.
- Methods for making semiconductor devices including localized semiconductor-on-insulator (soi) regions7 Nov 2024US 2024/0371883 A1Atomera Incorporated
- Semiconductor devices including localized semiconductor-on-insulator (soi) regions7 Nov 2024US 2024/0371943 A1Atomera Incorporated
- Source drain formation in gate all around transistor2 Mar 2023US 2023/0067331 A1APPLIED Materials.Inc.
Most cited
By later US patents
- Quantum well structures useful for semiconductor devices203US 5,216,262 A1993
- Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods117US 7,928,425 B2Mears Technologies, Inc. · 2011
- Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction116US 7,229,902 B2RJ Mears, LLC · 2007
- Semiconductor device including a superlattice and replacement metal gate structure and related methods77US 10,084,045 B2Atomera Incorporated · 2018
- Thin film transistor60US 4,849,797 AHosiden Electronics Co., Ltd. · 1989