Cascade tunneling field effect transistors
AssigneePurdue Research Foundation
InventorsTillmann C. Kubis, Prasad Sarangapani
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Abstract
A tunnel field-effect transistor (TFET) includes a fin, an insulator layer, and at least one gate. The fin has a doped first region, a doped second region, and an interior region between the first region and the second region. The interior region is undoped or is more lightly doped than the first region and the second region. At least the interior region of the fin formed as a type II superlattice, wherein materials of the superlattice alternate vertically. The insulator layer is formed around the interior region. The gate is formed on at least a portion of the insulator region. The insulator layer and the at least one gate are configured to generate an inhomogeneous electrostatic potential within the interior region.
Claims20
A tunnel field-effect transistor (TFET) comprising:
- a fin have a doped first region, a doped second region, and an interior region between the first region and the second region, the interior region being undoped or more lightly doped than the first region and the second region, at least the interior region of the fin formed as a type II superlattice, wherein materials of the superlattice alternate vertically;
- an insulator layer formed around the interior region;
- at least one gate formed on at least a portion of the insulator region;
- wherein the insulator layer and the at least one gate are configured to generate an inhomogeneous electrostatic potential within the interior region.
A tunnel field-effect transistor (TFET) comprising:
- a fin have a doped first region, a doped second region, and an interior region between the first region and the second region, the interior region being undoped or more lightly doped than the first region and the second region, at least the interior region of the fin formed as a type II superlattice, wherein materials of the superlattice alternate vertically;
- an insulator layer formed around the interior region;
- at least one gate formed on at least a portion of the insulator region;
- wherein the fin extends in a current direction from the first region to the second region and through the interior region, wherein the insulator layer and the at least one gate are configured to apply an electric field perpendicular to the current direction when voltage is applied to the at least one gate.
Dependencies are inferred from the claim text.