Methods of forming bottom dielectric isolation layers

A processing method comprising:

• recessing a plurality of channel layers in a superlattice structure to remove a depth of channel material and form a plurality of recessed channel layers, the superlattice structure on a dummy material, the superlattice structure comprising the plurality of channel layers and a corresponding plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs extending between a source trench and a drain trench, the plurality of semiconductor material layers comprising silicon (Si), the plurality of channel layers comprising silicon-germanium (SiGe), and the dummy material comprising silicon doped with a dopant selected from one or more of boron, phosphorus, arsenic, or germanium, the concentration of dopant in a range of from 2 atomic percent to 10 atomic percent;
• forming a conformal liner having a thickness over the plurality of recessed channel layers, the plurality of semiconductor material layers and the dummy material;
• removing the liner from the dummy material without exposing the plurality of recessed channel layers or the plurality of semiconductor material layers;
• removing the dummy material;
• etching the liner to expose the plurality of semiconductor material layers;
• depositing a bottom dielectric isolation layer under the superlattice structure;
• and
• depositing a silicon material on the bottom dielectric isolation layer to fill the superlattice structure.