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US 12,727,214 B2Granted
Source drain formation in gate all around transistor
AssigneeApplied Materials, Inc.
InventorsAshish Pal, El Mehdi Bazizi, Benjamin Colombeau
Life of this patent
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Abstract
Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is etched and then crystallized. Epitaxially growth of the source and drain regions then proceeds, with growth advantageously occurring on the bottom and sidewalls of the source and drain regions.
Claims20
A method of forming a semiconductor device, the method comprising:
- forming a gate structure on a superlattice structure, the superlattice structure on a top surface of a semiconductor substrate and comprising a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs;
- depositing a dielectric spacer layer on the gate structure and on the superlattice structure;
- removing a portion of the dielectric spacer layer to expose the plurality of horizontal channel layers and the plurality of semiconductor material layers;
- forming a source trench and a drain trench adjacent to the superlattice structure;
- forming a bottom dielectric isolation layer under the source trench and the drain trench and under the superlattice structure;
- forming an inner spacer layer on the plurality of semiconductor material layers of the superlattice structure;
- laterally etching a portion of the inner spacer layer to form a recessed region between the plurality of horizontal channel layers;
- depositing a template material continuously on the superlattice structure, in the recessed region, on the dielectric spacer layer, and in the source trench and in the drain trench;
- removing the template material from the dielectric spacer layer and leaving the template material in the recessed region;
- crystallizing the template material and the plurality of horizontal channel layers by one or more of rapid thermal processing (RTP) anneal or laser anneal;
- and
- forming a source region in the source trench on the bottom dielectric isolation layer and a drain region in the drain trench on the bottom dielectric isolation layer.
9 more elements
A method of forming a semiconductor device, the method comprising:
- forming a superlattice structure on a top surface of a bottom dielectric isolation layer on a substrate, the superlattice structure comprising a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs;
- forming a gate structure on a top surface of the superlattice structure;
- forming a dielectric layer on the gate structure and on the superlattice structure;
- forming a source trench and a drain trench adjacent to the superlattice structure on the bottom dielectric isolation layer on the substrate;
- forming an inner spacer layer on the plurality of semiconductor material layers of the superlattice structure;
- laterally etching a portion of the inner spacer layer to form a recessed region between the plurality of horizontal channel layers;
- depositing a template material continuously on the superlattice structure, in the recessed region, on the dielectric layer, and in the source trench and in the drain trench;
- removing the template material from the dielectric layer and leaving the template material in the recessed region on the inner spacer layer;
- annealing the substrate to crystallize the template material and the plurality of horizontal channel layers by one or more of rapid thermal processing (RTP) anneal or laser anneal;
- and
- forming a source region in the source trench on the bottom dielectric isolation layer and a drain region in the drain trench on the bottom dielectric isolation layer.
8 more elements
A method of forming a semiconductor device, the method comprising:
- laterally etching a portion of an inner spacer layer on a plurality of semiconductor material layers of a superlattice structure, the superlattice structure comprising a plurality of horizontal channel layers and the plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs, the superlattice structure on a bottom dielectric isolation layer extending between a source trench and a drain trench, wherein laterally etching the portion of the inner spacer forms a recessed region between the plurality of horizontal channel layers;
- depositing a template material continuously on the superlattice structure, in the recessed region, and in the source trench and in the drain trench;
- removing a portion of the template material but leaving the template material in the recessed region on the inner spacer layer;
- annealing the substrate to crystallize the template material and the plurality of horizontal channel layers by one or more of rapid thermal processing (RTP) anneal or laser anneal;
- and
- forming a source region in the source trench on the bottom dielectric isolation layer and a drain region in the drain trench on the bottom dielectric isolation layer.
3 more elements
Dependencies are inferred from the claim text.