H10D 30/6748
Having a multilayer structure or superlattice structure
Official title: {having a multilayer structure or superlattice structure}
H10D30/6748 (Having a multilayer structure or superlattice structure) appears on 461 US grants and 483 published applications in this corpus.
Search patents in H10D- Granted patents
- 461
- Published applications
- 483
- Assignees
- 115
- Inventors
- 694
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1987 | 1 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 1 | 0 |
| 1991 | 1 | 0 |
| 1992 | 1 | 0 |
| 1993 | 3 | 0 |
| 1994 | 1 | 0 |
| 1995 | 1 | 0 |
| 1996 | 1 | 0 |
| 1997 | 1 | 0 |
| 1998 | 3 | 0 |
| 1999 | 4 | 0 |
| 2000 | 1 | 0 |
| 2001 | 5 | 3 |
| 2002 | 7 | 9 |
| 2003 | 8 | 15 |
| 2004 | 24 | 39 |
| 2005 | 27 | 65 |
| 2006 | 37 | 66 |
| 2007 | 48 | 41 |
| 2008 | 30 | 42 |
| 2009 | 33 | 16 |
| 2010 | 34 | 13 |
| 2011 | 23 | 24 |
| 2012 | 16 | 14 |
| 2013 | 14 | 16 |
| 2014 | 19 | 13 |
| 2015 | 18 | 15 |
| 2016 | 23 | 18 |
| 2017 | 11 | 11 |
| 2018 | 14 | 9 |
| 2019 | 9 | 11 |
| 2020 | 10 | 3 |
| 2021 | 4 | 5 |
| 2022 | 2 | 7 |
| 2023 | 4 | 16 |
| 2024 | 6 | 6 |
| 2025 | 6 | 5 |
| 2026 | 9 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Semiconductor device with active layers doped by sacrificial layers and method thereof29 Sep 2026US 12,751,064 B2Samsung Electronics Co., Ltd.
- Etching compositions1 Sep 2026US 12,727,412 B2Fujifilm Electronic Materials U.S.A., Inc.
- Multi-layered or graded semiconductor region in thin film transistor (TFT) structures5 May 2026US 12,622,018 B2Intel Corporation
- Backside power rail to deep vias21 Apr 2026US 12,610,587 B2APPLIED Materials.Inc.
- Template for nanosheet source drain formation with bottom dielectric24 Mar 2026US 12,588,248 B2APPLIED Materials.Inc.
- Three-dimensional memory array comprising stacked oxide semiconductors in hybrid channel2 Jul 2026US 2026/0190322 A1SK hynix Inc.
- Seam-top seal for dielectrics27 Nov 2025US 2025/0366044 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Ferroelectric field effect transistor, memory device, and neural network device31 Jul 2025US 2025/0248074 A1Samsung Electronics Co., Ltd.
- Gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness13 Mar 2025US 2025/0089312 A1Intel Corporation
- Wrap around backside contact for s/d with backside trench epi and bspdn6 Mar 2025US 2025/0081541 A1International Business Machines Corporation
Most cited
By later US patents
- Method of manufacturing a substrate using an SiGe layer600US 6,607,948 B1Kabushiki Kaisha Toshiba · 2003
- Method of forming a double gate transistor having an epitaxial silicon/germanium channel region580US 6,475,869 B1Advanced Micro Devices, Inc. · 2002
- Semiconductor method and device with mixed orientation substrate566US 7,298,009 B2Infineon Technologies AG · 2007
- Strained-semiconductor-on-insulator device structures396US 6,995,430 B2AmberWave Systems Corporation · 2006
- Strained silicon fin structure325US 7,115,945 B2Sharp Laboratories of America, Inc. · 2006