Template for nanosheet source drain formation with bottom dielectric

A method of forming a semiconductor device, the method comprising:

• forming a superlattice structure on a top surface of a bottom dielectric isolation layer on a substrate, the superlattice structure comprising a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs and the bottom dielectric isolation layer selected from the group consisting of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-κ material;
• forming a gate structure on a top surface of the superlattice structure;
• forming a dielectric layer on the gate structure and on the superlattice structure;
• forming a source trench and a drain trench adjacent to the superlattice structure on the bottom dielectric isolation layer on the substrate;
• depositing a template material in the source trench and in the drain trench directly on the bottom dielectric isolation layer;
• annealing the substrate by one or more of rapid thermal processing (RTP) anneal or laser anneal at a temperature in a range of from 600° C. to 900° C. in an atmosphere of hydrogen (H2) gas and oxygen (O2) to crystallize the template material to form a crystallized template material directly on the bottom dielectric isolation layer;
• and
• forming a source region and a drain region on the crystallized template material.