Multi-layered or graded semiconductor region in thin film transistor (TFT) structures

An integrated circuit, comprising:

• a plurality of semiconductor devices;
• an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers;
• a thin film transistor (TFT) structure across one or more interconnect layers of the plurality of stacked interconnect layers, the TFT structure comprising
• a gate electrode,
• a gate dielectric on the gate electrode,
• a semiconductor region on the gate dielectric, wherein the semiconductor region includes a first semiconductor layer on the gate dielectric, a second semiconductor layer over the first semiconductor layer, and a third layer over the second semiconductor layer, and
• first and second conductive contacts that extend through a thickness of the third layer and land on a top surface of the second semiconductor layer.

An integrated circuit, comprising:

• a plurality of semiconductor devices;
• an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers;
• a thin film transistor (TFT) structure across one or more interconnect layers of the plurality of stacked interconnect layers, the TFT structure comprising
• a gate electrode,
• a gate dielectric on the gate electrode,
• a semiconductor layer on the gate dielectric, wherein the semiconductor layer has a material concentration gradient extending from a bottom surface of the semiconductor layer adjacent to the gate dielectric to a top surface of the semiconductor layer, and
• first and second conductive contacts that each contact a respective portion of the semiconductor layer.