Backside power rail to deep vias

A method of forming a semiconductor device, the method comprising:

• forming a superlattice structure on a top surface of a substrate, the superlattice structure comprising a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs;
• forming a gate structure on a top surface of the superlattice structure;
• forming a plurality of source regions and a plurality of drain regions adjacent to the superlattice structure on the substrate;
• forming a contact to transistor (CT) and a contact to gate (CG) in electrical contact with the plurality of source regions and the plurality of drain regions;
• forming a via opening adjacent to the superlattice structure and the gate structure and extending from an upper surface of the substrate to a top surface of the gate structure, the via opening having an aspect ratio that is greater than or equal to 10:1;
• depositing a metal in the via opening;
• bonding the semiconductor device to a bonding wafer;
• thinning the substrate;
• and
• forming a through-silicon-via (TSV) to a chip on one or more of a top surface of the semiconductor device or a bottom surface of the semiconductor device.