Gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness

Abstract

Gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, and methods of fabricating gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, are described. For example, an integrated circuit structure includes a nanowire with an outer thickness and an inner thickness, the inner thickness less than the outer thickness. The nanowire tapers from outer regions having the outer thickness to an inner region having the inner thickness. A dielectric material is on and surrounding the nanowire such that a combined thickness of the nanowire and the dielectric material in the inner region is approximately the same as the outer thickness of the nanowire.

Dependencies are inferred from the claim text.