Three-dimensional memory array comprising stacked oxide semiconductors in hybrid channel

A semiconductor memory device comprising:

• a substrate;
• a plurality of hybrid channel layers stacked in a vertical direction to the substrate, wherein each hybrid channel layer comprises high bandgap oxide semiconductor layers and a high mobility oxide semiconductor layer disposed between the high bandgap oxide semiconductor layers;
• a plurality of laterally oriented double word lines with each of the hybrid channel layers interposed between each of the double word lines;
• a vertically oriented bit line commonly connected to first ends of the high bandgap oxide semiconductor layers and a first end of the high mobility oxide semiconductor layer;
• and
• capacitors respectively connected to second ends of the high bandgap oxide semiconductor layers and a second end of the high mobility oxide semiconductor layer.

A semiconductor memory device, comprising:

• a substrate;
• and
• a three-dimensional array of memory cells over the substrate,
• wherein individual memory cells in the three-dimensional array comprise a transistor and a capacitor,
• wherein a channel of the transistor includes an inner oxide semiconductor layer disposed between two outer oxide semiconductor layers, and
• wherein the capacitor is connected to both an end of the inner oxide semiconductor layer and ends of the two outer oxide semiconductor layers.