G11C 2211/564
Miscellaneous aspects
G11C2211/564 (Miscellaneous aspects) appears on 2,898 US grants and 2,805 published applications in this corpus.
Search patents in G11C- Granted patents
- 2,898
- Published applications
- 2,805
- Assignees
- 312
- Inventors
- 2,843
- Latest grant
- 8 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1979 | 1 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 1 | 0 |
| 1984 | 1 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 2 | 0 |
| 1992 | 5 | 0 |
| 1993 | 6 | 0 |
| 1994 | 3 | 0 |
| 1995 | 6 | 0 |
| 1996 | 18 | 0 |
| 1997 | 17 | 0 |
| 1998 | 47 | 0 |
| 1999 | 53 | 0 |
| 2000 | 59 | 0 |
| 2001 | 49 | 23 |
| 2002 | 49 | 32 |
| 2003 | 29 | 41 |
| 2004 | 32 | 41 |
| 2005 | 27 | 45 |
| 2006 | 29 | 49 |
| 2007 | 49 | 95 |
| 2008 | 69 | 158 |
| 2009 | 102 | 151 |
| 2010 | 103 | 143 |
| 2011 | 139 | 118 |
| 2012 | 157 | 121 |
| 2013 | 127 | 119 |
| 2014 | 130 | 121 |
| 2015 | 132 | 106 |
| 2016 | 126 | 106 |
| 2017 | 118 | 101 |
| 2018 | 114 | 102 |
| 2019 | 132 | 192 |
| 2020 | 153 | 160 |
| 2021 | 181 | 179 |
| 2022 | 155 | 192 |
| 2023 | 168 | 171 |
| 2024 | 174 | 122 |
| 2025 | 101 | 79 |
| 2026 | 34 | 38 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
- G11C 2211/5641Multilevel memory having cells with different number of storage levelsIndexing code1,341
- G11C 2211/5642Multilevel memory with buffers, latches, registers at input or outputIndexing code786
- G11C 2211/5648Multilevel memory programming, reading or erasing operations wherein the order or sequenceIndexing code413
- G11C 2211/5644Multilevel memory comprising counting devicesIndexing code297
- G11C 2211/5643Multilevel memory comprising cache storage devicesIndexing code225
- G11C 2211/5646Multilevel memory with flag bitsIndexing code202
- G11C 2211/5647Multilevel memory with bit inversion arrangementIndexing code127
- G11C 2211/565Multilevel memory comprising elements in triple well structureIndexing code99
Recent patents
- Lifetime mixed level non-volatile memory system8 Sep 2026US 12,731,638 B2Vervain, LLC
- Data compression25 Aug 2026US 12,717,475 B2Samsung Electronics Co., Ltd.
- Flash memory for reducing reliability degradation of OS data due to SMT process and method for operating the same25 Aug 2026US 12,717,494 B2Samsung Electronics Co., Ltd.
- NAND die with wire-bond inductive compensation for altered bond wire bandwidth in memory devices25 Aug 2026US 12,718,878 B2SanDisk Technologies LLC
- Asymmetric pass through voltage for reduction of cell-to-cell interference11 Aug 2026US 12,704,969 B2Micron Technology, Inc.
- Method and apparatus for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory17 Sep 2026US 2026/0279460 A1Silicon Motion, Inc.
- Method and apparatus for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory17 Sep 2026US 2026/0279461 A1Silicon Motion, Inc.
- Memory system and information processing system27 Aug 2026US 2026/0252249 A1Kioxia Corporation
- Switched capacitance pull-down network for multi-level sensing in a memory device20 Aug 2026US 2026/0245630 A1Micron Technology, Inc.
- Memory sub-system for memory cell in-field touch-up13 Aug 2026US 2026/0236178 A1Micron Technology, Inc.
Most cited
By later US patents
- Multi-state EEprom read and write circuits and techniques1,175US 5,172,338 ASunDisk Corporation · 1992
- Multi-state EEPROM having write-verify control circuit972US 5,570,315 AKabushiki Kaisha Toshiba · 1996
- Semiconductor device and memory system940US 6,046,935 AKabushiki Kaisha Toshiba · 2000
- High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates827US 5,867,429 ASanDisk Corporation · 1999
- Highly compact EPROM and flash EEPROM devices819US 5,095,344 A1992