G11C 2211/5649
Multilevel memory with plate line or layer
Official title: Multilevel memory with plate line or layer, e.g. in order to lower programming voltages
G11C2211/5649 (Multilevel memory with plate line or layer) appears on 16 US grants and 16 published applications in this corpus.
Search patents in G11C- Granted patents
- 16
- Published applications
- 16
- Assignees
- 9
- Inventors
- 32
- Latest grant
- 21 Jan 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1999 | 2 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 0 |
| 2002 | 1 | 1 |
| 2003 | 0 | 0 |
| 2004 | 0 | 0 |
| 2005 | 0 | 0 |
| 2006 | 0 | 1 |
| 2007 | 2 | 3 |
| 2008 | 3 | 2 |
| 2009 | 0 | 2 |
| 2010 | 1 | 0 |
| 2011 | 3 | 1 |
| 2012 | 0 | 0 |
| 2013 | 0 | 1 |
| 2014 | 0 | 1 |
| 2015 | 1 | 1 |
| 2016 | 0 | 0 |
| 2017 | 0 | 0 |
| 2018 | 1 | 0 |
| 2019 | 0 | 0 |
| 2020 | 0 | 0 |
| 2021 | 0 | 0 |
| 2022 | 0 | 0 |
| 2023 | 0 | 2 |
| 2024 | 1 | 1 |
| 2025 | 1 | 0 |
By publication year. Applications have been published since 2001.
Recent patents
- Hybrid smart verify for QLC/TLC die21 Jan 2025US 12,205,657 B2SanDisk Technologies LLC
- Two-side staircase pre-charge in sub-block mode of three-tier non-volatile memory architecture6 Feb 2024US 11,894,072 B2SanDisk Technologies LLC
- Rank-modulation rewriting codes for flash memories13 Mar 2018US 9,916,197 B2California Institute of Technology
- Rank-modulation rewriting codes for flash memories21 Jul 2015US 9,086,955 B2California Institute of Technology
- Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells28 Jun 2011US 7,969,784 B2Kabushiki Kaisha Toshiba
- Hybrid smart verify for qlc/tlc die29 Feb 2024US 2024/0071524 A1SanDisk Technologies LLC
- Two-side staircase pre-charge in sub-block mode of three-tier non-volatile memory architecture26 Oct 2023US 2023/0343400 A1SanDisk Technologies LLC
- Three dimension memory device16 Mar 2023US 2023/0085583 A1Macronix International Co., Ltd.
- Rank-modulation rewriting codes for flash memories12 Nov 2015US 2015/0324253 A1California Institute of Technology
- Memory devices and methods having write data permutation for cell wear reduction27 Mar 2014US 2014/0089560 A1Adesto Technologies Corporation
Most cited
By later US patents
- High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates827US 5,867,429 ASanDisk Corporation · 1999
- Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells274US 6,373,746 B1Kabushiki Kaisha Toshiba · 2002
- Non-volatile memory device with NAND type cell structure71US 5,936,887 ASamsung Electronics Co., Ltd. · 1999
- Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells34US 7,177,196 B2Kabushiki Kaisha Toshiba · 2007
- Semiconductor memory device for storing multilevel data30US 7,471,559 B2Kabushiki Kaisha Toshiba · 2008