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US 2014/0089560 A1Published application
Memory devices and methods having write data permutation for cell wear reduction
AssigneeAdesto Technologies Corporation
InventorsRavi Sunkavalli, Malcolm Wing
Life of this patent
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Abstract
A memory system can include a plurality of memory elements each comprising a memory layer having at least one layer programmable between at least two different impedance states; a data input configured to receive multi-bit write data values; and a permutation circuit coupled between the memory elements and the data input, and configured to repeatedly permute the multi-bit write data values prior to writing such data values into the memory elements.
Claims20
A memory system, comprising:
- a plurality of memory elements each comprising a memory element having at least one layer programmable between at least two different impedance states;
- a data input configured to receive multi-bit write data values;
- and
- a permutation circuit coupled between the memory elements and the data input, and configured to repeatedly permute the multi-bit write data values prior to writing such data values into the memory elements.
1 more element
A method, comprising:
- permuting bits of write data written into memory cells having at least one programmable impedance layer;
- and
- repeatedly changing a permutation type in response to a wear limit for at least a portion of the memory cells.
A memory system, comprising:
- a plurality of memory elements each comprising a memory layer having at least one memory layer programmable between at least two different impedance states;
- a permutation circuit configured to permute bits of write data written into the memory elements in response to permutation select data;
- and
- a nonvolatile store to store the permutation select data.
1 more element
Dependencies are inferred from the claim text.