Semiconductor memory device for storing multilevel data
AssigneeKabushiki Kaisha Toshiba
InventorNoboru Shibata
Life of this patent
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Abstract
In a memory cell array, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells stores one of a plurality of threshold levels. When writing one of the plurality of threshold levels into a first memory cell of the memory cell array, a control circuit writes a threshold level a little lower than the original threshold level. When not writing a second memory cell adjacent to the first memory cell consecutively, the control circuit writes the original threshold level into the first memory cell.
Claims18
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells are arranged in a matrix, each of said plurality of memory cells storing one of a plurality of threshold levels;
- and
- a control circuit which, when writing one of said plurality of threshold levels into a first memory cell of the memory cell array, writes a threshold level lower than an original threshold level, and which, when not writing a second memory cell adjacent to the first memory cell consecutively, writes the original threshold level into the first memory cell.
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells are arranged in a matrix, each of said plurality of memory cells storing one of a plurality of threshold levels;
- and
- a control circuit which, when writing one of said plurality of threshold levels into a first memory cell of the memory cell array and further writing a second memory cell adjacent to the first memory cell consecutively, writes a threshold level lower than an original threshold level and which, when not writing the second memory cell adjacent to the first memory cell consecutively, writes the first memory cell at a decreased write speed.
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells are arranged in a matrix, each of said plurality of memory cells storing one of a plurality of threshold levels;
- and
- a control circuit which, when writing one of said plurality of threshold levels into a first memory cell of the memory cell array, writes a threshold level lower than an original threshold level and which, when not writing a second memory cell adjacent to the first memory cell consecutively, keeps the first memory cell at the lower threshold level and, when writing one of said plurality of threshold levels into the second memory cell, reads the threshold level from the first memory cell and, after writing a specific threshold level into the second memory cell, writes the original threshold level into the first memory cell on the basis of the result of the reading.
Dependencies are inferred from the claim text.