Two-side staircase pre-charge in sub-block mode of three-tier non-volatile memory architecture
AssigneeSanDisk Technologies LLC
InventorsJiacen Guo, Xiang Yang, Abhijith Prakash
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AssigneeSanDisk Technologies LLC
InventorsJiacen Guo, Xiang Yang, Abhijith Prakash
Estimating the term…
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings. A control means is coupled to the word lines and the strings and is configured to ramp a voltage applied to a selected one of the word lines from a verify voltage to a reduced voltage during a program-verify portion of a program operation. The control means successively ramps voltages applied to each of a plurality of neighboring ones of the word lines from a read pass voltage to the reduced voltage beginning with ones of the plurality of neighboring ones of the word lines immediately adjacent the selected one of the word lines and progressing to ones of the plurality of neighboring others of the word lines disposed increasingly remotely from the selected one of the word lines during the program-verify portion of the program operation.
A memory apparatus, comprising:
A controller in communication with a memory apparatus including memory cells each connected to one of a plurality of word lines and disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states, the controller configured to:
A method of operating a memory apparatus including memory cells each connected to one of a plurality of word lines and disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states, the method comprising the steps of:
Dependencies are inferred from the claim text.