Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells
AssigneeKabushiki Kaisha Toshiba
InventorsKen Takeuchi, Tomoharu Tanaka, Noboru Shibata
Life of this patent
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Abstract
Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.
Claims5
A nonvolatile semiconductor memory comprising:
- NAND strings each comprised of memory cells connected in series;
- control gate lines which are connected to control gates of the memory cells of the NAND strings respectively;
- bit lines which is connected to the NAND strings respectively;
- data circuits which is connected to the bit lines respectively, each of the data circuits stored data which indicates a write enable or a write inhibit;
- and
- a control circuit executing a program completion detection which detects the completion of the programming based on the data, during supplying a program potential to the control gate line of the selected memory cell,
- wherein a predetermined number or more of the data circuits indicate the write inhibit, when the programming is completed.
Dependencies are inferred from the claim text.