Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells

A nonvolatile semiconductor memory comprising:

• a first string line including a first memory and a first select transistor connected in series;
• a second string line including a second memory cell and a second select transistor connected in series;
• a first bit line connected to said first string line;
• a second bit connected to said second string line, being different from said first bit line;
• a common node connnected to one ends of said first and second bit lines;
• and
• a common latch circuit connected to said common node,
• wherein
• said first and second memory cells are programmed substantially simultaneously;
• while a program voltage is supplied to said first memory cell, program data of said memory cell is held by second bit line, and while said program voltage is supplied to said second memory cell, the program data of said first memory cell held by said first bit line is latched in said common latch circuit and a verify read operation to verify whether said first memory cell has been programmed sufficiently, is carried out by said common latch circuit;
• while said program is supplied to said first memory cell, program data of said first memory cell is held by said first bit line, and while said program voltage is supplied to said first memory cell, the program of data said second memory cell held by said second memory cell has been programmed sufficiently, is carried out by said common latch circuit.

A nonvolatile semiconductor memory comprising:

• a first string line including a first memory cell and a first select transistor connected in series;
• a first bit line connected to said first string line;
• a second bit line, being different from said first bit line;
• a common node connected to one ends of said first and second bit lines latching program/read data;
• and
• a common latch circuit connected to said common node,
• wherein
• while a program voltage is supplied to said first memory cell, program data of said first memory cell is held by at least one of said first and second bit lines;
• after said program voltage is supplied to said first memory cell, said common latch circuit is electrically connected to said second bit line and the program data of said first memory cell held by said second bit line is latched in said common latch circuit;
• and
• a verify read operation to verify whether said first memory cell has been sufficiently programmed, is carried out using said program data latched in said common latch circuit.

A nonvolatile semiconductor memory comprising:

• a first string line including a first memory cell and a first select transistor connected in series;
• a first bit line connected to said first string line;
• a second string line including a second memory cell and a second select transistor connected in series;
• a third bit line connected to said second string line;
• a fourth bit line;
• a common node connected to one ends of said first, second, third and fourth bit lines, latching program/read data of at least one of said first and second memory cells;
• and
• a common latch circuit connected to said common node,
• wherein
• said first, second, third and fourth bit lines are different from each other;
• said first and second memory cells are programmed substantially simultaneously, program data of said first memory cell is held by at least one of said first and second bit lines, and program data of said second memory cell is held by at least one of said third and fourth bit lines while a program voltage is supplied to said first and second memory cells;
• a verify read operation to verify whether said first memory cell has been sufficiently programmed, is carried out by said common latch circuit, and program data of said second memory cell is held by said fourth bit line while conducting the verify read operation of said first memory cell;
• and
• said common latch circuit and said fourth bit line are electrically connected to each other, after the program data of said second memory cell held by said fourth bit line is latched in said common latch circuit, a verify read operation to verify whether said second memory cell has been sufficiently programmed, is carried out using the program data of said second memory cell held by said common latch circuit, and while conducting a verify read operation of said second memory cell, the program data of said first memory cell is held by said second bit line.

A nonvolatile semiconductor memory comprising:

• a first memory cell section including a first memory cell;
• a first signal line connected to said first memory cell section;
• a second signal line;
• a third memory cell section including a third memory cell;
• a third signal line connected to said third memory cell section;
• a fourth signal line;
• and
• a data circuit connected to one ends of said first, second, third and forth signal lines, and including a latch circuit said latch circuit latching program/read data of at least one of said first and third memory cells;
• wherein
• said first and third memory cells are programmed substantially simultaneously, program data of said first memory cell is held by at least one of said first and second signal lines, and program data of said third memory cell is held by at least one of said third and fourth signal lines while a program voltage is supplied to said first and second memory cells;
• a verify read operation to verify whether said first memory cell has been sufficiently programmed, is carried out by said latch circuit, and program data of said third memory cell is held by said fourth signal line while conducting the verify read operation of said first memory cell;
• and
• said data circuit and said fourth signal line are electrically connected to each other, after the program data of said third memory cell held by said fourth signal line is latched in said latch circuit, a verify read operation to verify whether said third memory cell has been sufficiently programmed, is carried out using the program data of said third memory cell held by said latch circuit, and while conducting a verify read operation of said third memory cell, the program data of said first memory cell is held by said second signal line.