G11C 2211/5647

Multilevel memory with bit inversion arrangement

G11C2211/5647 (Multilevel memory with bit inversion arrangement) appears on 127 US grants and 118 published applications in this corpus.

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Granted patents
127
Published applications
118
Assignees
54
Inventors
169
Latest grant
18 Mar 2025

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G11C 2211/5647: granted patents and published applications per publication year
YearGranted patentsPublished applications
199110
199200
199300
199400
199500
199600
199710
199810
199920
200070
200141
200221
2003010
2004106
200563
200622
200735
2008512
2009811
2010910
2011108
201267
2013812
2014137
201565
201655
201753
201841
201912
202013
202121
202222
202311
202410
202510

By publication year. Applications have been published since 2001.

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