Nonvolatile memory device and memory system including nonvolatile memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsBEOMKYU SHIN, SUNGKYU PARK
Life of this patent
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Abstract
A nonvolatile memory device performs a compare and write operation. The compare and write operation includes reading read data from memory cells, inverting first write data to generate second write data, adding a first flag bit to the first write data to generate third write data and adding a second flag bit to the second write data to generate fourth write data, performing a reinforcement operation on each of the third write data and the fourth write data to generate fifth write data and sixth write data, and comparing the read data with each of the fifth write data and the sixth write data and writing one of the fifth and sixth write data in the memory cells based on a result of the comparison.
Claims20
A nonvolatile memory device comprising:
- a plurality of memory cells;
- a read circuit configured to receive first read data and second read data from the plurality of memory cells;
- an inversion circuit configured to receive first write data from an external device, and to invert the first write data to generate second write data;
- a flag bit adding circuit configured to receive the first write data from the external device and the second write data from the inversion circuit, to add a first flag bit to the second write data to generate third write data, and to add a second flag bit to the first write data to generate fourth write data;
- a compare and write circuit configured to receive the first read data, the third write data and the fourth write data, to perform a first comparison between the first read data and the third write data, to perform a second comparison between the first read data and the fourth write data, to select one of the third write data and the fourth write data based on a result of the first comparison and the second comparison, and to write the selected one of the third write data and the fourth write data in the plurality of memory cells;
- and
- a flag bit detection circuit configured to receive the second read data from the read circuit, and either configured to output the second read data to the external device or configured to generate third read data by removing at least one flag bit from the second read data and output the third read data to the inversion circuit,
- wherein if the inversion circuit receives the third read data from the flag bit detection circuit, the inversion circuit is configured to invert the third read data to generate fourth read data, and configured to output the fourth read data to the external device.
A nonvolatile memory device comprising:
- a plurality of memory cells;
- an inversion circuit configured to receive first write data from an external device, and to invert the first write data to generate second write data;
- a flag bit adding circuit configured to receive the first write data from the external device and the second write data from the inversion circuit, to add a first flag bit to the second write data to generate third write data, and to add a second flag bit to the first write data to generate fourth write data;
- and
- a compare and write circuit configured to receive first read data stored in the plurality of memory cells, the third write data and the fourth write data, to perform a first comparison between the first read data and the third write data, to perform a second comparison between the first read data and the fourth write data, to select one of the third write data and the fourth write data based on a result of the first comparison and the second comparison, and to write the selected one of the third write data and the fourth write data in the plurality of memory cells.
A nonvolatile memory device comprising:
- a plurality of memory cells;
- an inversion circuit configured to receive first write data, and to invert the first write data to generate second write data;
- a flag bit adding circuit configured to receive the first write data and the second write data, to add a first flag bit to the second write data to generate third write data, and to add a second flag bit to the first write data to generate fourth write data;
- and
- a compare and write circuit configured to receive the third write data and the fourth write data, to select one of the third write data and the fourth write data, and to write the selected one of the third write data and the fourth write data in the plurality of memory cells.
Dependencies are inferred from the claim text.