A memory controller for reading data stored in a flash memory, the memory controller comprising:
- a receiving circuit, arranged for receiving a plurality of bit sequences corresponding to a plurality of memory cells from the flash memory;
- an error correction code (ECC) circuit, arranged for performing a decoding operation upon the bit sequences;
- and
- a control logic, coupled to the receiving circuit and the ECC circuit;
- wherein when the decoding operation fails, the control logic controls the flash memory to perform a plurality of read operations;
- wherein when finding a first best control gate voltage, the control logic adjusts a first initial control gate voltage according to a first voltage spacing to perform the read operations;
- and
- when finding a second best control gate voltage, the control logic adjusts a second initial control gate voltage according to a second voltage spacing to perform the read operations;
- wherein the first voltage spacing is adjustable, and the first voltage spacing is different from the second voltage spacing.