Method and apparatus for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory
AssigneeSilicon Motion, Inc.
InventorTsung-Chieh Yang
Life of this patent
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Abstract
A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.
Claims6
A memory controller for reading data stored in a flash memory, the memory controller comprising:
- a receiving circuit, arranged for receiving a plurality of bit sequences corresponding to a plurality of memory cells from the flash memory;
- an error correction code (ECC) circuit, arranged for performing a decoding operation upon the bit sequences;
- and
- a control logic, coupled to the receiving circuit and the ECC circuit;
- wherein when the decoding operation fails, the control logic controls the flash memory to perform a plurality of read operations upon the memory cells to obtain updated bit sequences by utilizing a first plurality of voltage settings corresponding to a first initial control gate voltage and a second plurality of voltage settings corresponding to a second initial control gate voltage;
- wherein the control logic determines a first shifting direction of the first initial control gate voltage and a second shifting direction of the second initial control gate voltage simultaneously in a parallel processing manner according to a bit flipping information of the updated bit sequences.
A method for reading data stored in a flash memory, comprising:
- receiving a plurality of bit sequences corresponding to a plurality of memory cells from the flash memory;
- performing an error correction code (ECC) decoding operation upon the bit sequences;
- when the decoding operation fails, performing a plurality of read operations upon the memory cells to obtain updated bit sequences by utilizing a first plurality of voltage settings corresponding to a first initial control gate voltage and a second plurality of voltage settings corresponding to a second initial control gate voltage;
- and
- determining a first shifting direction of the first initial control gate voltage and a second shifting direction of the second initial control gate voltage simultaneously in a parallel processing manner according to a bit flipping information of the updated bit sequences.
Dependencies are inferred from the claim text.