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US 5,172,338 AGranted
Multi-state EEprom read and write circuits and techniques
AssigneeSunDisk Corporation
InventorsSanjay Mehrotra, Eliyahou Harari, Winston Lee
Life of this patent
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AssigneeSunDisk Corporation
InventorsSanjay Mehrotra, Eliyahou Harari, Winston Lee
Estimating the term…
Improvements in the circuits and techniques for read, write and erase of EEprom memory enable non-volatile multi-state memory to operate with enhanced performance over an extended period of time. In the improved circuits for normal read, and read between write or erase for verification, the reading is made relative to a set of threshold levels as provided by a corresponding set of reference cells which closely track and make adjustment for the variations presented by the memory cells. In one embodiment, each Flash sector of memory cells has its own reference cells for reading the cells in the sector, and a set of reference cells also exists for the whole memory chip acting as a master reference. In another embodiment, the reading is made relative to a set of threshold levels simultaneously by means of a one-to-many current mirror circuit. In improved write or erase circuits, verification of the written or erased data is done in parallel on a group of memory cells at a time and a circuit selectively inhibits further write or erase to those cells which have been correctly verified. Other improvements includes programming the ground state after erase, independent and variable power supply for the control gate of EEprom memory cells.
In an integrated circuit memory system having an array of a plurality of addressable semiconductor electrically erasable and programmable memory (EEprom) cells of the type having a source, a drain, a control gate, a floating gate capable of retaining a charge level programmed into it during use of the memory system, resulting in a definite memory state having a corresponding threshold of conduction relative to a set of predetermined threshold levels used to demarcate memory states, and an erase electrode capable of removing charge from said floating gate, said array of EEprom cells being organized into one or more sectors of cells, where cells in each sector are erasable simultaneously, and said memory system including a reading system for determining the programmed state of an addressed cell in a given sector, said reading system comprising:
In an integrated circuit memory system having an array of a plurality of addressable semiconductor electrically erasable and programmable memory (EEprom) cells of the type having a source, a drain, a control gate, a floating gate capable of retaining a charge level programmed into it during use of the memory system resulting in a memory state having a corresponding threshold of conduction, and an erase electrode capable of removing charge from said floating gate, said array of EEprom cells being organized into one or more sectors of cells, where cells in each sector are erasable simultaneously, and said memory system including a reading system for determining the programmed threshold of an addressed cell relative to each of a set of predetermined thresholds used to demarcate memory states, said reading system comprising:
In an integrated circuit memory system having an array of a plurality of addressable semiconductor electrically erasable and programmable memory (EEprom) cells of the type having a source, a drain, a control gate, a floating gate capable of retaining a charge level programmed into it during use of the memory system, resulting in a definite memory state having a corresponding threshold of conduction relative to at least two predetermined threshold levels used to demarcate memory states, and an erase electrode capable of removing charge from said floating gate, and said memory system including a reading system for determining the programmed state of an addressed cell, said reading system comprising:
In an array of a plurality of addressable semiconductor electrically erasable and programmable memory cells of the type having a source, a drain, a control gate, a floating gate capable of retaining a charge level programmed into it during use of the memory, and an erase electrode capable of removing charge from said floating gate, a system for reading the stored charge of an addressed cell within two ranges defined by one predetermined threshold level, comprising:
In an array of a plurality of addressable semiconductor electrically erasable and programmable memory cells of the type having a source, a drain, a conductance between the source and drain that is controlled by the level of charge programmed onto a floating gate, and having a control gate and an erase electrode, a system for reading the state of an addressed cell by measuring the level of current passing therethrough, comprising:
An EEprom memory system on an integrated circuit chip, comprising:
In an array of addressable semiconductor electrically erasable and programmable memory (EEprom) cells on an integrated circuit chip, the memory cell being of the type having a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, such that a specific memory state is achieved by increment or decrement of the charge level with successive applications of programming or erasing voltage conditions, a system for programming data to EEprom cells including means for temporarily storing a chunk of data for programming a plurality of addressed cells, means for programming in parallel the stored chunk of data into the plurality of addressed cells, and means for verifying the programmed data in each of the plurality of addressed cells with the chunk of stored data, wherein the improvement comprises:
In an array of addressable semiconductor electrically erasable and programmable memory (EEprom) cells on an integrated circuit chip, the memory cells being of the type having a source, a drain, a control gate and an erase electrode receptive to specific voltages for reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, such that a specific memory state is achieved by increment or decrement of the charge level with successive applications of programming or erasing voltage conditions, a system residing on the EEprom integrated circuit chip for programming data to EEprom cells including means for temporarily storing a chunk of data for programming a plurality of addressed EEprom cells, means for programming in parallel the stored chunk of data into the plurality of addressed EEprom cells, and means for verifying the programmed data in each of the plurality of addressed EEprom cells with the chunk of stored data, wherein the improvement comprises:
In an array of addressable semiconductor electrically erasable and programmable memory (EEprom) cells on an integrated circuit chip, the memory cells being of the type having a source, a drain, a control gate and an erase electrode receptive to specific voltages for reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, such that a specific memory state is achieved by increment or decrement of the charge level with successive applications of programming or erasing voltage conditions, a system residing on the EEprom integrated circuit chip for programing data to EEprom cells including means for temporarily storing a chunk of data for programming a plurality of addressed EEprom cells, means for programming in parallel the stored chunk of data into the plurality of addressed EEprom cells, and means for verifying the programmed data in each of the plurality of addressed EEprom cells with the chunk of stored data, wherein the improvement comprises:
In an array of addressable semiconductor electrically erasable and programmable memory (EEprom) cells on an integrated circuit chip, the memory cells being of the type having a source, a drain, a control gate and an erase electrode receptive to specific voltages for reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, such that a specific memory state is achieved by increment or decrement of the charge level with successive applications of programming or erasing voltage conditions, a system residing on the EEprom integrated circuit chip for programming data to EEprom cells including means for temporarily storing a chunk of data for programming a plurality of addressed cells, means for programming in parallel the stored chunk of data into the plurality of addressed cells, and means for verifying the programmed data in each of the plurality of addressed cells with the chunk of stored data, wherein the improvement comprises:
In an array of addressable semiconductor electrically erasable and programmable memory (EEprom) cells on an integrated circuit chip, the memory cell being of the type having a source, a drain, a control gate and an erase electrode receptive to specific voltages for reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, such that a specific memory state is achieved by increment or decrement of the charge level with successive applications of programming or erasing voltage conditions, a system for erasing the EEprom cells including means for erasing in parallel a plurality of addressed EEprom cells, means for verifying the memory state in each of the plurality of addressed EEprom cells, means for enabling further erasing in parallel to one or more of the addressed EEprom cells until all the plurality of addressed EEprom cells are verified to be in an erased state, said verifying means includes a system for reading the stored charge of an addressed cell within ranges defined by one or more predetermined threshold levels, wherein the improvement in said system for reading comprising:
In an array of addressable semiconductor electrically erasable and programmable memory (EEprom) cells on an integrated circuit chip, the memory cell being of the type having a source, a drain, a control gate and an erase electrode receptive to specific voltages for reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, such that a specific memory state is achieved by increment or decrement of the charge level with successive applications of programming or erasing voltage conditions, the memory cells are grouped such that all cells in the group are erasable simultaneously, a system for erasing the EEprom cells including means for erasing in parallel a plurality of addressed EEprom cells, means for verifying the memory state in each of the plurality of addressed EEprom cells, means for enabling further erasing in parallel to one or more of the addressed EEprom cells until all the plurality of addressed EEprom cells are verified to be in an erased state, said verifying means includes a reading circuit for reading the stored charge of an addressed cell within ranges defined by one or more predetermined threshold levels, wherein the improvement in said system for reading comprises:
In an array of addressable semiconductor electrically erasable and programmable memory (EEprom) cells on an integrated circuit chip, the memory cell being of the type having a source, a drain, a control gate and an erase electrode receptive to specific voltages for reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, such that a specific memory state is achieved by increment or decrement of the charge level with successive applications or programming or erasing voltage conditions, a system for erasing the EEprom cells including means for erasing in parallel a plurality of addressed EEprom cells, means for verifying the memory state in each of the plurality of addressed EEprom cells means for enabling further erasing in parallel to one or more of the addressed EEprom cells until all the plurality of addressed EEprom cells are verified to be in an erased state;
In an array of addressable semiconductor electrically erasable and programmable memory cells on an integrated circuit chip, the memory cell being of the type having a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, such that a specific memory state is achieved by increment or decrement of the charge level with successive applications of programming or erasing voltage conditions, a system for erasing the EEprom memory cells including means for erasing in parallel a plurality of addressed cells, means for verifying the memory state in each of the plurality of addressed cells, means for enabling further erasing in parallel to one or more of the addressed cells until all the plurality of addressed cells are verified to be in an erased state, wherein the improvement comprises:
In a EEprom system including an array of addressable semiconductor electrically erasable and programmable memory cells on an integrated circuit chip, a controller for controlling the operation of the memory cells, means for temporarily storing on chip a chunk of data transferred from the controller, means for programming in parallel the stored chunk of data into the plurality of addressed cells, means for verifying on chip the programmed data in each of the plurality of addressed cells with the chunk of stored data, means for enabling further programming in parallel to one or more of the addressed cells until all the plurality of addressed cells are verified, wherein the improvement in programming the plurality of addressed memory cells comprises:
In an integrated circuit memory system having an array of a plurality of addressable semiconductor electrically erasable and programmable memory (EEprom) cells of the type having a source, a drain, a control gate, a floating gate capable of retaining a charge level programmed into it during use of the memory system, resulting in a definite memory state having a corresponding threshold of conduction relative to one or more predetermined threshold levels used to demarcate memory states, and an erase electrode capable of removing charge from said floating gate, and said memory system including a reading system for determining the programmed state of an addressed cell, said reading system comprising:
Dependencies are inferred from the claim text.