G11C 2211/5642
Multilevel memory with buffers, latches, registers at input or output
G11C2211/5642 (Multilevel memory with buffers, latches, registers at input or output) appears on 786 US grants and 682 published applications in this corpus.
Search patents in G11C- Granted patents
- 786
- Published applications
- 682
- Assignees
- 94
- Inventors
- 817
- Latest grant
- 4 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1979 | 1 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 1 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 1 | 0 |
| 1994 | 0 | 0 |
| 1995 | 3 | 0 |
| 1996 | 6 | 0 |
| 1997 | 11 | 0 |
| 1998 | 25 | 0 |
| 1999 | 25 | 0 |
| 2000 | 35 | 0 |
| 2001 | 33 | 17 |
| 2002 | 32 | 21 |
| 2003 | 11 | 18 |
| 2004 | 17 | 17 |
| 2005 | 14 | 13 |
| 2006 | 10 | 15 |
| 2007 | 15 | 33 |
| 2008 | 22 | 39 |
| 2009 | 34 | 35 |
| 2010 | 27 | 33 |
| 2011 | 38 | 24 |
| 2012 | 31 | 21 |
| 2013 | 19 | 12 |
| 2014 | 17 | 13 |
| 2015 | 12 | 9 |
| 2016 | 10 | 6 |
| 2017 | 8 | 17 |
| 2018 | 19 | 22 |
| 2019 | 32 | 41 |
| 2020 | 29 | 34 |
| 2021 | 42 | 52 |
| 2022 | 50 | 64 |
| 2023 | 52 | 63 |
| 2024 | 51 | 35 |
| 2025 | 45 | 19 |
| 2026 | 8 | 9 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Compact data latches4 Aug 2026US 12,700,436 B2SanDisk Technologies LLC
- Pattern analysis enabled read operation in nand component16 Jun 2026US 12,658,266 B2SK hynix Inc.
- Second read initialization on latch-limited memory device26 May 2026US 12,638,990 B2Micron Technology, Inc.
- Page buffer circuit and memory device including the same24 Mar 2026US 12,586,650 B2Samsung Electronics Co., Ltd.
- Semiconductor storage device17 Mar 2026US 12,578,902 B2Kioxia Corporation
- Switched capacitance pull-down network for multi-level sensing in a memory device20 Aug 2026US 2026/0245630 A1Micron Technology, Inc.
- Nonvolatile memory device including cache latch address information and/or input/output pad address information and method of operating the same16 Jul 2026US 2026/0204318 A1Samsung Electronics Co., Ltd.
- Semiconductor storage device2 Jul 2026US 2026/0186703 A1Kioxia Corporation
- High bandwidth parallel program method with dynamic latch for three-dimensional memory array7 May 2026US 2026/0128098 A1Micron Technology, Inc.
- Enhanced io interface for plc program and program-suspend-resume operations9 Apr 2026US 2026/0100208 A1Intel NDTM US LLC
Most cited
By later US patents
- Multi-state EEPROM having write-verify control circuit972US 5,570,315 AKabushiki Kaisha Toshiba · 1996
- Semiconductor device and memory system940US 6,046,935 AKabushiki Kaisha Toshiba · 2000
- Multi-state non-volatile flash memory capable of being its own two state write cache505US 5,930,167 ASanDisk Corporation · 1999
- Programming method to reduce gate coupling interference for non-volatile memory460US 7,400,532 B2Micron Technology, Inc. · 2008
- Semiconductor device and memory system454US 5,903,495 AKabushiki Kaisha Toshiba · 1999