Semiconductor storage device

A semiconductor storage device, comprising:

• a memory string including a plurality of memory transistors connected in series;
• a bit line connected to the memory string;
• a sense amplifier connected to the bit line and including a first latch circuit and a second latch circuit;
• a cache memory connected to the sense amplifier and including a third latch circuit;
• and
• a control circuit configured to perform a first read operation in response to a first command set and then perform a second read operation in response to a second command set received during the first read operation, wherein
• during the first read operation, data read from the memory string is stored in the first latch circuit, and
• the control circuit performs a data transfer operation of transferring the data stored in the first latch circuit to the second latch circuit during the first read operation and then to the third latch circuit during the second read operation.

A semiconductor storage device, comprising:

• a plurality of memory strings, each of which includes a plurality of memory transistors connected in series;
• a plurality of word lines, each of which is connected to a gate electrode of one of the memory transistors in each of the memory strings;
• and
• a control circuit configured to perform a first read operation in response to a first command set and consecutively perform a second read operation in response to a second command set received during the first read operation, wherein
• when the first read operation is performed with respect to a first group of memory transistors connected to a selected one of the word lines, and the second read operation is performed with respect to a second group of memory transistors connected to the selected one of the word lines, the control circuit causes voltages of word lines that are not selected during the first read operation to be maintained when transitioning from the first read operation to the second read operation.