High bandwidth parallel program method with dynamic latch for three-dimensional memory array

A method performed by a three-dimensional memory device comprising a plurality of memory blocks having a first memory block, the first memory block including a plurality of sets of sub-blocks, the method comprising:

• causing a global bit line to rise to a global bit line voltage;
• activating one or more write transistors in each of a plurality of dynamic latch devices and activating a select gate of one sub-block in each set of sub-blocks of the plurality of sets of sub-blocks;
• causing word lines connected to a selected memory cell of a sub-block in each set of sub-blocks of the plurality of sets of sub-blocks to rise to a first word line voltage;
• causing word lines connected to unselected memory cells of the sub-block in each set of sub-blocks of the plurality of sets of sub-blocks to rise to a second word line voltage;
• deactivating one or more write transistors in each of the plurality of dynamic latch devices and activating another select gate of one sub-block in each set of sub-blocks of the plurality of sets of sub-blocks;
• and
• serially activating, for each of the plurality of dynamic latch devices, one or more read transistors, and causing multiple selected sub-blocks to be read using the plurality of dynamic latch device based on a single read pulse.

A method performed by a three-dimensional memory device comprising a plurality of memory blocks having a first memory block, the first memory block including a plurality of sets of sub-blocks, the method comprising:

• causing word lines connected to all sets of sub-blocks of the plurality of sets of sub-blocks to rise to a first word line voltage based on a single programming pulse, such that pillars of memory cells in the plurality sets of sub-blocks are charged up and floating;
• causing the global bit line to rise to a global bit line voltage;
• performing, for each sub-block in the plurality set of the plurality of sets sub-blocks:
• activating one or more write transistors in a dynamic latch device of a plurality of dynamic latch devices and activating a select gate of a sub-block in a corresponding set of sub-blocks of the plurality of sets of sub-blocks;
• modulating the global bit line voltage to remain the same or change based on program data;
• causing word lines connected to a selected sub-block in each set of sub-blocks of the plurality of sets of sub-blocks to rise to a second word line voltage;
• and
• programing multiple selected sub-blocks via the plurality of dynamic latches based on a single programming pulse.

A memory system comprising:

• a processor;
• and
• a memory device coupled to the processor, the memory device comprising:
• an array of memory cells comprising a plurality of memory blocks having a first memory block, the first memory block including a plurality of sets of sub-blocks;
• a global bit line;
• a controller;
• and
• a plurality of dynamic latch devices connected between the global bit line and the plurality of sets of sub-blocks, wherein:
• a first dynamic latch device of the plurality of dynamic latch devices is connected to a first set of sub-blocks of the plurality of sets of sub-blocks,
• different dynamic latch devices of the plurality of dynamic latch devices are connected to different sets of sub-blocks of the plurality of sets of sub-blocks, and
• the first dynamic latch device is controllable by the controller to store program data during a program operation in which the first set of sub-blocks connected to the first dynamic latch device are unselected sub-blocks during the program operation.