US 12,586,650 B2Granted

Page buffer circuit and memory device including the same

AssigneeSamsung Electronics Co., Ltd.

InventorsYongsung Cho, Insu Kim, Daeseok Byeon

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Abstract

A memory device includes a memory cell array, and a page buffer circuit including a plurality of page buffers selectively connected to memory cells via a plurality of bit lines, each of the plurality of page buffers including a sensing node. The sensing nodes may be charged to different levels during verification of programming states of the memory cells. For example, a first sensing node of a first page buffer connected to a first memory cell targeted for programming to a first program state from among the plurality of page buffers is precharged to a first level in a first precharge period during verification of the first program state. A second sensing node of a second page buffer connected to a second memory cell targeted for programming to a second program state charged to a second level during verification of the second program state, wherein the second level is different from the first level.

Claims20

Dependent claims

A memory device comprising:

a memory cell array comprising a plurality of memory cells respectively connected to a plurality of word lines;
a page buffer circuit connected to the memory cell array through a plurality of bit lines, including a first bit line and a second bit line, and comprising a plurality of page buffers each connected to a corresponding one of the plurality of bit lines, each of the plurality of page buffers comprising a corresponding sensing node, the page buffers including a first page buffer connected to a first memory cell via the first bit line and a second page buffer connected to a second memory cell via the second bit line;
the page buffer circuit configured to:
precharge a first sensing node of the first page buffer connected to the first memory cell to a first level in a first precharge period during verification of a first program state of the first memory cell, and
precharge a second sensing node of the second page buffer connected to the second memory cell to a second level in a second precharge period during verification of a second program state of the second memory cell, wherein the second level is different from the first level;
and
a row decoder configured to apply a verify voltage to a selected word line commonly connected to the first memory cell and the second memory cell during the first precharge period and the second precharge period, wherein a level of the verify voltage applied to the selected word line during the first precharge period and the second precharge period are same.

4 more elements

A memory device comprising:

a memory cell array comprising a plurality of memory cells;
a page buffer circuit connected to the memory cell array through a plurality of bit lines and comprising a plurality of page buffers each connected to a corresponding one of the plurality of bit lines, each of the plurality of page buffers comprising a boost node, a sensing node and a precharge circuit configured to precharge the sensing node to a first level during verification of a first program state and during verification of a second program state;
and
a boost voltage controller configured:
to apply to boost nodes of page buffers of memory cells selected for verification of the second program state, a boost voltage during verification of the second program state to increase a voltage level of sensing nodes of the page buffers from the first level to a second level higher than the first level, and
to not apply any boost voltage to boost nodes of the page buffers during verification of the first program state.

3 more elements

A page buffer circuit comprising a plurality of page buffers respectively corresponding to a plurality of bit lines,

wherein each of the plurality of page buffers comprises:
a sensing node formed in a first wiring layer selectively connected to a precharge circuit to be precharged to a first level during a verification operation, selectively connected to a corresponding bit line to be developed in a developing period, and selectively connected to a sensing latch to provide a voltage level of the sensing node in a sensing period to be compared with a reference voltage level;
and
a boost node formed in the first wiring layer configured to boost a voltage level of the sensing node when a boost voltage is applied during the verification operation,
wherein a wiring corresponding to the sensing node and a wiring corresponding to the boost node are located adjacent to each other in the first wiring layer and are capacitively coupled together.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/367,799Filed 13 Sep 2023
Priority: KR 10-2022-01446232 Nov 2022
Published: US 2024/0145013 A12 May 2024
Granted: 24 Mar 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G11C 11/5628
Using charge storage in a floating gate: programming or writing circuits; Data input circuits
G11C 16/24
Auxiliary circuits, e.g. for writing into memory: bit-line control circuits
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits