Nonvolatile memory device including cache latch address information and/or input/output pad address information and method of operating the same

Abstract

A nonvolatile memory device includes a memory cell array including a plurality of planes, a page buffer circuit connected to the memory cell array through a plurality of bitlines and comprising at least one cache latch, and a plurality of input/output pads connected to the page buffer circuit through a plurality of data lines and configured to transmit data to and receive data from a memory controller. A command set may include at least one of cache latch address information or input/output pad address information, and the nonvolatile memory device is configured to perform a readout operation or a write operation based on at least one of the cache latch address information or the input/output pad address information included in the command set.

Dependencies are inferred from the claim text.