Pattern analysis enabled read operation in nand component

A system, comprising:

• a memory;
• a wordline of memory cells configured to store data;
• control circuitry configured to:
• apply a first reference drive voltage to the wordline of memory cells to generate a respective first resulting voltage level from each respective cell in the wordline;
• for each respective first resulting voltage level output by each cell in the wordline, store in the memory a first respective logic value indicated by the respective first resulting voltage level;
• apply a second reference drive voltage to the wordline of memory cells to generate a respective second resulting voltage level from each respective cell in the wordline;
• detect a pattern of logic values stored in the memory;
• for each respective second resulting voltage level output by each cell in the wordline, modify the memory based on a second respective logic value indicated by the respective second resulting voltage level, wherein the circuitry is to modify the memory based on the second respective logic value by:
• storing results of bitwise logical operations between the second respective logic value and a corresponding logic value of the stored first logic values, wherein the bitwise logical operations between the second respective logic value and the corresponding logic value comprise negating the respective second logic value and performing a bitwise logical operation between the negated second logic value and the corresponding logic value;
• and
• modify at least one of the first reference drive voltage and the second reference drive voltage based on the detected pattern data.

A non-transitory computer readable medium having non-transitory computer readable instructions encoded thereon that, when executed by circuitry, cause the circuitry to:

• apply a first reference drive voltage to a wordline of memory cells to generate a respective first resulting voltage level from each respective cell in the wordline;
• for each respective first resulting voltage level output by each cell in the wordline, store in memory a first respective logic value indicated by the respective first resulting voltage level;
• apply a second reference drive voltage to the wordline of memory cells to generate a respective second resulting voltage level from each respective cell in the wordline;
• detect a pattern of logic values stored in the memory;
• for each respective second resulting voltage level output by each cell in the wordline, modify the memory based on a second respective logic value indicated by the respective second resulting voltage level, wherein the circuitry is to modify the memory based on the second respective logic value by:
• storing results of bitwise logical operations between the second respective logic value and a corresponding logic value of the stored first logic values, wherein the bitwise logical operations between the second respective logic value and the corresponding logic value comprise negating the respective second logic value and performing a bitwise logical operation between the negated second logic value and the corresponding logic value;
• and
• modify at least one of the first reference drive voltage and the second reference drive voltage based on the detected pattern data.