Programming method to reduce gate coupling interference for non-volatile memory

A method of programming memory cells of a non-volatile NAND architecture memory array, comprising:

• receiving a first write data and a second write data;
• selecting a first physical page of memory cells from a plurality of NAND architecture memory strings of the NAND architecture non-volatile memory array;
• and
• adjusting the programming of the first write data into the first physical page of memory cells to compensate for interference by the subsequent programming of the second write data into a second adjacent physical page of memory cells of the plurality of NAND architecture memory strings of the NAND architecture non-volatile memory array.

A NAND architecture non-volatile memory device, comprising:

• a NAND architecture non-volatile memory array having a plurality of non-volatile memory cells arranged in rows and columns, wherein the plurality of non-volatile memory cells are coupled into a plurality of NAND architecture memory cell strings;
• and
• a control circuit, wherein the control circuit is adapted to program a first write data into a first physical page of memory cells of the non-volatile memory array and a second write data into an adjacent second physical page of memory cells of the non-volatile memory array by,
• compensating the target threshold voltage levels of the first write data to be programmed into the first physical page of memory cells for interference due to the target threshold data values of a second data to be programmed into the adjacent second physical page;
• selecting the first physical page in one or more NAND architecture memory cell strings for programming of non-volatile memory array, where the selected memory cell in each of the one or more memory cell strings is coupled to a word line,
• applying a program voltage to the word line coupled to the selected memory cells of the first physical page,
• applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings, and
• verifying the adjusted threshold voltage values stored in the first physical page against the first write data.

A memory module, comprising:

• a plurality of contacts;
• and
• two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
• wherein at least one of the memory devices comprises:
• a NAND architecture non-volatile memory array having a plurality of non-volatile memory cells arranged in rows and columns and further arranged into a plurality of NAND architecture memory cell strings;
• wherein the non-volatile memory device is adapted to compensate a first write data to be programmed into a first physical page of memory cells for interference due to the subsequent programming of a second write data into a second physical page of memory cells of the array, where the second physical page is adjacent to the first physical page in the array.

A memory module, comprising:

• a housing having a plurality of contacts;
• and
• one or more non-volatile NAND architecture memory devices enclosed in the housing and selectively coupled to the plurality of contacts;
• wherein the memory module is adapted to program memory cells in a selected block of at least one of the non-volatile NAND architecture memory devices by,
• receiving a first write data and a second write data;
• selecting a first physical page of memory cells from a plurality of NAND architecture memory strings of the NAND architecture non-volatile memory array;
• and
• adjusting the programming of the first write data into the first physical page of memory cells to compensate for interference by the subsequent programming of the second write data into a second adjacent physical page of memory cells of the plurality of NAND architecture memory strings of the NAND architecture non-volatile memory array.