H10W 70/6528
Of the portions that connect to chips, wafers or package parts
Official title: {of the portions that connect to chips, wafers or package parts}
H10W70/6528 (Of the portions that connect to chips, wafers or package parts) appears on 1,303 US grants and 1,790 published applications in this corpus.
Search patents in H10W- Granted patents
- 1,303
- Published applications
- 1,790
- Assignees
- 214
- Inventors
- 2,100
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2001 | 1 | 1 |
| 2002 | 1 | 0 |
| 2003 | 0 | 0 |
| 2004 | 2 | 0 |
| 2005 | 0 | 0 |
| 2006 | 2 | 0 |
| 2007 | 0 | 1 |
| 2008 | 0 | 4 |
| 2009 | 1 | 3 |
| 2010 | 1 | 7 |
| 2011 | 2 | 6 |
| 2012 | 6 | 13 |
| 2013 | 6 | 17 |
| 2014 | 21 | 19 |
| 2015 | 10 | 24 |
| 2016 | 21 | 16 |
| 2017 | 30 | 37 |
| 2018 | 27 | 69 |
| 2019 | 101 | 158 |
| 2020 | 128 | 181 |
| 2021 | 142 | 252 |
| 2022 | 175 | 294 |
| 2023 | 196 | 199 |
| 2024 | 187 | 193 |
| 2025 | 168 | 195 |
| 2026 | 75 | 101 |
By publication year. 2026 runs to 8 Oct.
Recent patents
- Method of manufacturing semiconductor packages6 Oct 2026US 12,757,759 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Multiple plated via arrays of different wire heights on a same substrate6 Oct 2026US RE51,062 E1Adeia Semiconductor Technologies LLC
- Substrate employing core with cavity embedding reduced height electrical device(s), and related integrated circuit (IC) packages and fabrication methods29 Sep 2026US 12,751,306 B2QUALCOMM Incorporated
- Die package structure and method for forming the same29 Sep 2026US 12,751,314 B2Winbond Electronics Corp.
- Semiconductor device15 Sep 2026US 12,740,429 B2Renesas Electronics Corporation
- Flip-chip package with pre-molded leadframe8 Oct 2026US 2026/0314454 A1Navitas Semiconductor Limited
- Integrated Circuit Package With Improved Heat Dissipation Efficiency and Methods of Forming the Same8 Oct 2026US 2026/0314492 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Methods of Forming Packages and Resulting Structures8 Oct 2026US 2026/0314493 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor package with alignment marks1 Oct 2026US 2026/0305371 A1Samsung Electronics Co., Ltd.
- Package structure and method of manufacturing the same1 Oct 2026US 2026/0305458 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Stacked semiconductor devices and methods of forming same1,870US 9,496,189 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Methods and apparatus of wafer level package for heterogeneous integration technology1,051US 9,111,949 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2015
- Hermetic wafer scale integrated circuit structure79US 6,982,475 B1Mcsp, LLC · 2006
- 3D chip-on-wafer-on-substrate structure with via last process63US 9,698,081 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2017
- Semiconductor device and method61US 10,340,249 B1Taiwan Semiconductor Manufacturing Company.Ltd · 2019