3D chip-on-wafer-on-substrate structure with via last process

A package comprising:

• a first die comprising:
• a first semiconductor substrate;
• first redistribution layers (RDLs) comprising a first conductive element;
• a conductive via extending through the first semiconductor substrate and the first RDLs;
• and
• a first spacer disposed between a sidewall of the conductive via and a sidewall of the first semiconductor substrate;
• a second die bonded to the first die, wherein the second die comprises:
• a second semiconductor substrate;
• and
• second RDLs directly bonded to the first RDLs and comprising a second conductive element, wherein the conductive via extends from the first conductive element to the second conductive element;
• and
• an insulating film extending along sidewalls of the first die, wherein the insulating film extends across an interface between the first spacer and the first semiconductor substrate.

A semiconductor package comprising:

• a first semiconductor substrate;
• first redistribution layers (RDLs) over the first semiconductor substrate, wherein the first RDLs comprise a first conductive line;
• second RDLs over and bonded to the first RDLs, wherein the second RDLs comprise a second conductive line;
• a second semiconductor substrate over the second RDLs;
• an insulation film over and extending along sidewalls of second semiconductor substrate and the second RDLs;
• a conductive via extending from a top surface of the insulating film to the first conductive line and the second conductive line;
• a first spacer disposed between the conductive via and the second semiconductor substrate;
• and
• a second spacer between the first spacer and the second semiconductor substrate, wherein the second spacer extends through the second semiconductor substrate, and wherein the insulating film is disposed directly over the second spacer.