Semiconductor package with alignment marks

A semiconductor package comprising:

• an interposer substrate;
• and
• a first semiconductor chip on the interposer substrate;
• and
• a second semiconductor chip on the interposer substrate,
• wherein the first semiconductor chip and the second semiconductor chip are spaced apart from each other in a first direction parallel to a surface of the interposer substrate, and
• wherein the interposer substrate comprises:
• an alignment mark on the surface of the interposer substrate;
• and
• a first metal block overlapping the alignment mark in a second direction perpendicular to the surface of the interposer substrate,
• wherein the alignment mark has a first area,
• wherein the first metal block has a second area,
• wherein the second area is greater than the first area, and
• wherein the alignment mark is located within the first metal block.

A semiconductor package comprising:

• a package substrate;
• an interposer substrate on the package substrate;
• a first semiconductor chip on the interposer substrate;
• and
• a chip stack structure spaced apart from the first semiconductor chip in a first direction parallel to a surface of the interposer substrate,
• wherein the chip stack structure comprises:
• a second semiconductor chip;
• and
• third semiconductor chips stacked on the second semiconductor chip in a second direction perpendicular to the surface of the interposer substrate;
• wherein the second semiconductor chip and the third semiconductor chips each include through vias,
• wherein the interposer substrate comprises:
• a first redistribution layer;
• a second redistribution layer on the first redistribution layer;
• and
• a connection layer between the first redistribution layer and the second redistribution layer,
• wherein the connection layer comprises:
• a connection die;
• a conductive pillar spaced apart from the connection die in the first direction;
• and
• a mold layer covering a surface of the connection die and a surface of the conductive pillar,
• wherein the second redistribution layer comprises:
• a first bonding pad connected to the first semiconductor chip;
• a second bonding pad connected to the second semiconductor chip;
• an alignment mark located at a same level as the first bonding pad and the second bonding pad in the second direction;
• a first metal block overlapping the alignment mark in the second direction;
• and
• a second metal block overlapping the alignment mark in the second direction with the first metal block between the second metal block and the alignment mark,
• wherein the alignment mark comprises:
• a via;
• and
• a plate on the via,
• wherein a surface of the via is in contact with a surface of the first metal block,
• wherein the first metal block is spaced apart from the second metal block, and
• wherein a height of the via is equal to or greater than a distance between a surface of the second metal block and a surface of the first metal block,
• wherein the plate has first surfaces facing in the first direction,
• wherein the first metal block has second surfaces opposite each other,
• wherein the second metal block has third surfaces opposite each other, and
• wherein the second surfaces and the third surfaces are located outside of the first surfaces.