H10W 70/08
By depositing layers on the chip or wafer
Official title: by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
H10W70/08 (By depositing layers on the chip or wafer) appears on 7,129 US grants and 8,821 published applications in this corpus.
Search patents in H10W- Granted patents
- 7,129
- Published applications
- 8,821
- Assignees
- 747
- Inventors
- 6,502
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 1 | 0 |
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 2 | 0 |
| 1991 | 3 | 0 |
| 1992 | 1 | 0 |
| 1993 | 1 | 0 |
| 1994 | 2 | 0 |
| 1995 | 2 | 0 |
| 1996 | 2 | 0 |
| 1997 | 2 | 0 |
| 1998 | 3 | 0 |
| 1999 | 6 | 0 |
| 2000 | 10 | 0 |
| 2001 | 11 | 3 |
| 2002 | 13 | 21 |
| 2003 | 18 | 28 |
| 2004 | 32 | 59 |
| 2005 | 32 | 72 |
| 2006 | 40 | 83 |
| 2007 | 44 | 77 |
| 2008 | 45 | 162 |
| 2009 | 70 | 179 |
| 2010 | 121 | 194 |
| 2011 | 161 | 227 |
| 2012 | 161 | 260 |
| 2013 | 220 | 288 |
| 2014 | 277 | 370 |
| 2015 | 290 | 451 |
| 2016 | 419 | 457 |
| 2017 | 506 | 553 |
| 2018 | 530 | 538 |
| 2019 | 592 | 675 |
| 2020 | 612 | 804 |
| 2021 | 584 | 728 |
| 2022 | 559 | 713 |
| 2023 | 543 | 522 |
| 2024 | 533 | 611 |
| 2025 | 483 | 521 |
| 2026 | 194 | 225 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Method of manufacturing semiconductor packages6 Oct 2026US 12,757,759 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor devices and methods of making semiconductor devices having embedded photonic bridge die6 Oct 2026US 12,757,798 B2STATS ChipPAC Pte. Ltd.
- Substrate employing core with cavity embedding reduced height electrical device(s), and related integrated circuit (IC) packages and fabrication methods29 Sep 2026US 12,751,306 B2QUALCOMM Incorporated
- Semiconductor package and semiconductor package assembly with edge side interconnection29 Sep 2026US 12,751,308 B2Etron Technology, Inc.
- Die package structure and method for forming the same29 Sep 2026US 12,751,314 B2Winbond Electronics Corp.
- Manufacturing method of the semiconductor package8 Oct 2026US 2026/0314301 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Layered molded direct contact and dielectric structure and method for making the same8 Oct 2026US 2026/0314434 A1Deca Technologies USA, Inc.
- Semiconductor Device and Method of Making Using a Die and Pillar First Approach8 Oct 2026US 2026/0314473 A1STATS ChipPAC Pte. Ltd.
- Semiconductor device and methods of manufacture8 Oct 2026US 2026/0314490 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Integrated Circuit Package With Improved Heat Dissipation Efficiency and Methods of Forming the Same8 Oct 2026US 2026/0314492 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Method of fabricating interconnect structure for package-on-package devices1,078US 9,048,222 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2015
- Methods and apparatus of wafer level package for heterogeneous integration technology1,051US 9,111,949 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2015
- Packaged semiconductor device with a molding compound and a method of forming the same1,039US 9,000,584 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2015
- Fan-out interconnect structure and method for forming same1,030US 9,368,460 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Package with metal-insulator-metal capacitor and method of manufacturing the same1,021US 9,263,511 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016