Semiconductor package and semiconductor package assembly with edge side interconnection

A semiconductor package, comprising:

• a plurality of integrated circuit (IC) structures, each IC structure comprising:
• a first body having a primary surface and a secondary surface, wherein the primary surface is greater than the secondary surface in area;
• and
• a primary redistribution layer (RDL) over the primary surface of the first body, with the primary RDL having an edge surface aligned or substantially aligned with the secondary surface of the first body;
• and
• an edge RDL over the secondary surface of the first body of each IC structure and the edge surface of the primary RDL of each IC structure,
• wherein the primary RDL is electrically connected to the edge RDL and the first body, and the edge RDL is electrically connected to the first body through the primary RDL,
• wherein the primary RDL further comprises a first conductive element exposed through the edge surface of the primary RDL, wherein the first conductive element comprises a conductive pad on the edge surface of the primary RDL substantially parallel to the primary surface, a conductive via connecting adjacent layers of the primary RDL, a stacked via traversing the primary RDL, or a combination thereof.

A semiconductor package, comprising:

• a plurality of integrated circuit (IC) structures, each IC structure comprising:
• a first body having a primary surface and a secondary surface, wherein the primary surface is greater than the secondary surface in area;
• and
• a primary redistribution layer (RDL) over the primary surface of the first body, with the primary RDL having an edge surface aligned or substantially aligned with the secondary surface of the first body;
• and
• an edge RDL over the secondary surface of the first body of each IC structure and the edge surface of the primary RDL of each IC structure,
• wherein the primary RDL is electrically connected to the edge RDL and the first body, and the edge RDL is electrically connected to the first body through the primary RDL,
• wherein the secondary surface of the first body and the edge surface of the primary RDL jointly form a secondary plane, wherein the edge RDL covers the secondary plane, with the edge RDL comprising a first surface coincident with the secondary plane, and a second surface opposite to the first surface, wherein the first surface of the edge RDL comprises a first flip-chip bonding layer corresponding to a second flip-chip bonding layer on the secondary plane.