H10D 84/985
Two levels of metal
Official title: {Two levels of metal}
H10D84/985 (Two levels of metal) appears on 48 US grants and 42 published applications in this corpus.
Search patents in H10D- Granted patents
- 48
- Published applications
- 42
- Assignees
- 20
- Inventors
- 120
- Latest grant
- 25 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2012 | 0 | 1 |
| 2013 | 1 | 2 |
| 2014 | 2 | 2 |
| 2015 | 3 | 0 |
| 2016 | 1 | 2 |
| 2017 | 9 | 3 |
| 2018 | 6 | 3 |
| 2019 | 4 | 4 |
| 2020 | 3 | 3 |
| 2021 | 3 | 3 |
| 2022 | 2 | 4 |
| 2023 | 3 | 3 |
| 2024 | 3 | 6 |
| 2025 | 6 | 5 |
| 2026 | 2 | 1 |
By publication year. 2026 runs to 8 Oct.
Recent patents
- VTFET circuit with optimized MOL25 Aug 2026US 12,720,860 B2International Business Machines Corporation
- Integrated circuit including standard cells, and method of designing the integrated circuit28 Apr 2026US 12,615,847 B2Samsung Electronics Co., Ltd.
- Integrated circuit and method of forming the same21 Oct 2025US 12,450,416 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Cooling device semiconductor device including end curved interconnection lines12 Aug 2025US 12,389,676 B2Samsung Electronics Co., Ltd.
- Integrated circuit device with improved layout27 May 2025US 12,315,862 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Cell region having vg-contact-free and vd-contact-free tracks and method of manufacturing same2 Apr 2026US 2026/0096208 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Integrated circuit and method of forming the same13 Nov 2025US 2025/0348652 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Integrated circuit device with improved layout13 Nov 2025US 2025/0351572 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Power rail and signal conducting line arrangement4 Sep 2025US 2025/0280600 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device31 Jul 2025US 2025/0248116 A1Samsung Electronics Co., Ltd.
Most cited
By later US patents
- Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods30US 9,035,359 B2Tela Innovations, Inc. · 2015
- Integrated circuit containing DOEs of NCEM-enabled fill cells17US 9,799,575 B2PDF Solutions, Inc. · 2017
- Method to ensure double patterning technology compliance in standard cells11US 8,756,550 B2Texas Instruments Incorporated · 2014
- Complementary metal oxide semiconductor (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods9US 9,978,682 B1QUALCOMM Incorporated · 2018
- Integrated circuit layout structure6US 10,290,653 B2United Microelectronics Corp. · 2019