Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods

A method for creating a layout of an integrated circuit for a semiconductor chip, comprising:

• operating a computer to define a layout of a region including layout features of at least seventeen linear-shaped conductive structures oriented to extend lengthwise in a first direction, each of the at least seventeen linear-shaped conductive structures having a corresponding lengthwise centerline oriented in the first direction,
• each of the at least seventeen linear-shaped conductive structures positioned such that a distance as measured in a second direction between its lengthwise centerline and the lengthwise centerline of at least one other of the at least seventeen linear-shaped conductive structures is substantially equal to a first pitch, the second direction perpendicular to the first direction, the first pitch being less than 193 nanometers, each of the at least seventeen linear-shaped conductive structures having a corresponding width as measured in the second direction that is less than 193 nanometers, each of the at least seventeen linear-shaped conductive structures having a corresponding co-planar top surface when manufactured,
• the at least seventeen linear-shaped conductive structures including a first linear-shaped conductive structure, and a second linear-shaped conductive structure, and a third linear-shaped conductive structure, and a fourth linear-shaped conductive structure, and a fifth linear-shaped conductive structure, and a sixth linear-shaped conductive structure,
• the first linear-shaped conductive structure including a portion that forms a gate electrode of a first transistor of a first transistor type, the first linear-shaped conductive structure also including a portion that forms a gate electrode of a first transistor of a second transistor type,
• the second linear-shaped conductive structure including a portion that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second linear-shaped conductive structure is of the first transistor type,
• the third linear-shaped conductive structure including a portion that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third linear-shaped conductive structure is of the second transistor type,
• the fourth linear-shaped conductive structure including a portion that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth linear-shaped conductive structure is of the first transistor type,
• the fifth linear-shaped conductive structure including a portion that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth linear-shaped conductive structure is of the second transistor type,
• the sixth linear-shaped conductive structure including a portion that forms a gate electrode of a fourth transistor of the first transistor type, the sixth linear-shaped conductive structure also including a portion that forms a gate electrode of a fourth transistor of the second transistor type,
• the lengthwise centerline of the second linear-shaped conductive structure substantially aligned with the lengthwise centerline of the third linear-shaped conductive structure, the lengthwise centerline of the fourth linear-shaped conductive structure substantially aligned with the lengthwise centerline of the fifth linear-shaped conductive structure,
• the first, second, third, and fourth transistors of the first transistor type being part of a collection of transistors of the first transistor type within the region,
• the first, second, third, and fourth transistors of the second transistor type being part of a collection of transistors of the second transistor type within the region,
• the collection of transistors of the first transistor type separated from the collection of transistors of the second transistor type by an inner region that does not include a source or a drain of any transistor,
• the first, second, third, and fourth transistors of the first transistor type and the first, second, third, and fourth transistors of the second transistor type involved in implementation of a particular logic function,
• the layout feature of the second linear-shaped conductive structure including an electrical connection area for physical connection with another conductive structure involved in implementation of the particular logic function, the electrical connection area of the second linear-shaped conductive structure being the only portion of the second linear-shaped conductive structure above a substrate of the semiconductor chip that is to be in physical connection with another conductive structure involved in implementation of the particular logic function,
• the layout feature of the third linear-shaped conductive structure including an electrical connection area for physical connection with another conductive structure involved in implementation of the particular logic function, the electrical connection area of the third linear-shaped conductive structure being the only portion of the third linear-shaped conductive structure above the substrate of the semiconductor chip that is to be in physical connection with another conductive structure involved in implementation of the particular logic function,
• the layout feature of the fourth linear-shaped conductive structure including an electrical connection area for physical connection with another conductive structure involved in implementation of the particular logic function, the electrical connection area of the fourth linear-shaped conductive structure being the only portion of the fourth linear-shaped conductive structure above the substrate of the semiconductor chip that is to be in physical connection with another conductive structure involved in implementation of the particular logic function,
• the layout feature of the fifth linear-shaped conductive structure including an electrical connection area for physical connection with another conductive structure involved in implementation of the particular logic function, the electrical connection area of the fifth linear-shaped conductive structure being the only portion of the fifth linear-shaped conductive structure above the substrate of the semiconductor chip that is to be in physical connection with another conductive structure involved in implementation of the particular logic function,
• one of the electrical connection area of the second linear-shaped conductive structure and the electrical connection area of the fourth linear-shaped conductive structure is located within the inner region, and
• one of the electrical connection area of the third linear-shaped conductive structure and the electrical connection area of the fifth linear-shaped conductive structure is located within the inner region, and
• one of the electrical connection area of the second linear-shaped conductive structure and the electrical connection area of the fourth linear-shaped conductive structure is located outside the inner region, or
• one of the electrical connection area of the third linear-shaped conductive structure and the electrical connection area of the fifth linear-shaped conductive structure is located outside the inner region, or both 1) one of the electrical connection area of the second linear-shaped conductive structure and the electrical connection area of the fourth linear-shaped conductive structure is located outside the inner region and 2) one of the electrical connection area of the third linear-shaped conductive structure and the electrical connection area of the fifth linear-shaped conductive structure is located outside the inner region.

A data storage device having program instructions stored thereon for generating a layout of an integrated circuit for a semiconductor chip, comprising:

• program instructions for defining a layout of a region including layout features of at least seventeen linear-shaped conductive structures oriented to extend lengthwise in a first direction, each of the at least seventeen linear-shaped conductive structures having a corresponding lengthwise centerline oriented in the first direction,
• each of the at least seventeen linear-shaped conductive structures positioned such that a distance as measured in a second direction between its lengthwise centerline and the lengthwise centerline of at least one other of the at least seventeen linear-shaped conductive structures is substantially equal to a first pitch, the second direction perpendicular to the first direction, the first pitch being less than 193 nanometers, each of the at least seventeen linear-shaped conductive structures having a corresponding width as measured in the second direction that is less than 193 nanometers, each of the at least seventeen linear-shaped conductive structures having a corresponding co-planar top surface when manufactured,
• the at least seventeen linear-shaped conductive structures including a first linear-shaped conductive structure, and a second linear-shaped conductive structure, and a third linear-shaped conductive structure, and a fourth linear-shaped conductive structure, and a fifth linear-shaped conductive structure, and a sixth linear-shaped conductive structure,
• the first linear-shaped conductive structure including a portion that forms a gate electrode of a first transistor of a first transistor type, the first linear-shaped conductive structure also including a portion that forms a gate electrode of a first transistor of a second transistor type,
• the second linear-shaped conductive structure including a portion that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second linear-shaped conductive structure is of the first transistor type,
• the third linear-shaped conductive structure including a portion that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third linear-shaped conductive structure is of the second transistor type,
• the fourth linear-shaped conductive structure including a portion that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth linear-shaped conductive structure is of the first transistor type,
• the fifth linear-shaped conductive structure including a portion that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth linear-shaped conductive structure is of the second transistor type,
• the sixth linear-shaped conductive structure including a portion that forms a gate electrode of a fourth transistor of the first transistor type, the sixth linear-shaped conductive structure also including a portion that forms a gate electrode of a fourth transistor of the second transistor type,
• the lengthwise centerline of the second linear-shaped conductive structure substantially aligned with the lengthwise centerline of the third linear-shaped conductive structure, the lengthwise centerline of the fourth linear-shaped conductive structure substantially aligned with the lengthwise centerline of the fifth linear-shaped conductive structure,
• the first, second, third, and fourth transistors of the first transistor type being part of a collection of transistors of the first transistor type within the region,
• the first, second, third, and fourth transistors of the second transistor type being part of a collection of transistors of the second transistor type within the region,
• the collection of transistors of the first transistor type separated from the collection of transistors of the second transistor type by an inner region that does not include a source or a drain of any transistor,
• the first, second, third, and fourth transistors of the first transistor type and the first, second, third, and fourth transistors of the second transistor type involved in implementation of a particular logic function,
• the layout feature of the second linear-shaped conductive structure including an electrical connection area for physical connection with another conductive structure involved in implementation of the particular logic function, the electrical connection area of the second linear-shaped conductive structure being the only portion of the second linear-shaped conductive structure above a substrate of the semiconductor chip that is to be in physical connection with another conductive structure involved in implementation of the particular logic function,
• the layout feature of the third linear-shaped conductive structure including an electrical connection area for physical connection with another conductive structure involved in implementation of the particular logic function, the electrical connection area of the third linear-shaped conductive structure being the only portion of the third linear-shaped conductive structure above the substrate of the semiconductor chip that is to be in physical connection with another conductive structure involved in implementation of the particular logic function,
• the layout feature of the fourth linear-shaped conductive structure including an electrical connection area for physical connection with another conductive structure involved in implementation of the particular logic function, the electrical connection area of the fourth linear-shaped conductive structure being the only portion of the fourth linear-shaped conductive structure above the substrate of the semiconductor chip that is to be in physical connection with another conductive structure involved in implementation of the particular logic function,
• the layout feature of the fifth linear-shaped conductive structure including an electrical connection area for physical connection with another conductive structure involved in implementation of the particular logic function, the electrical connection area of the fifth linear-shaped conductive structure being the only portion of the fifth linear-shaped conductive structure above the substrate of the semiconductor chip that is to be in physical connection with another conductive structure involved in implementation of the particular logic function,
• one of the electrical connection area of the second linear-shaped conductive structure and the electrical connection area of the fourth linear-shaped conductive structure is located within the inner region, and
• one of the electrical connection area of the third linear-shaped conductive structure and the electrical connection area of the fifth linear-shaped conductive structure is located within the inner region, and
• one of the electrical connection area of the second linear-shaped conductive structure and the electrical connection area of the fourth linear-shaped conductive structure is located outside the inner region, or
• one of the electrical connection area of the third linear-shaped conductive structure and the electrical connection area of the fifth linear-shaped conductive structure is located outside the inner region, or both 1) one of the electrical connection area of the second linear-shaped conductive structure and the electrical connection area of the fourth linear-shaped conductive structure is located outside the inner region and 2) one of the electrical connection area of the third linear-shaped conductive structure and the electrical connection area of the fifth linear-shaped conductive structure is located outside the inner region.